From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 584BBC83F0A for ; Wed, 9 Jul 2025 18:45:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1858D10E096; Wed, 9 Jul 2025 18:45:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="c+EKGWfC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22CF510E35C for ; Wed, 9 Jul 2025 18:45:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752086744; x=1783622744; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CT33h1N1+/NZgzXT82IG5P1X9TywDEOZ/eCkm3W2oFY=; b=c+EKGWfCkHeFSVbf8EaUdFq+Mwh+bw32tz63on8OP1C58ShzGAurFAKL BCL2uszcyo4aKpNO+QXeGqF+myeUokWXCOS73G8X7NOOg2TO0e/AxLJ1n 60ZHZdHp5G7it9UUJAKvitf0YvzHGioYASCS205Cpe+b7KSt3gLoTqcW8 D+7aftxulumJRqsm9EQWOSkgv6VGwa9uNKqSyYyapkLzzcBZJwkDpRzYv an4PBwyy4Qt8t4Ra2S6YQ8CtblGrG2Ypj/++a5gjaHt6nUGTLlEcLabf5 OOGVFhsOQL+7ALkpkPC02y0JZ5qyYQ8vl2jZvgSKRtrcl7uLRPVjtnoQ2 g==; X-CSE-ConnectionGUID: b6TzSvRLSkuJXe5PWBC62Q== X-CSE-MsgGUID: 5HFSp4uUSb+gUgARdWIpwg== X-IronPort-AV: E=McAfee;i="6800,10657,11489"; a="54451103" X-IronPort-AV: E=Sophos;i="6.16,298,1744095600"; d="scan'208";a="54451103" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2025 11:45:44 -0700 X-CSE-ConnectionGUID: Wwr8bpoTRiiOfEkiTwLsJw== X-CSE-MsgGUID: vbSuERkiQ02PzKvu7OUiQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,298,1744095600"; d="scan'208";a="161404895" Received: from mjruhl-desk.amr.corp.intel.com (HELO mjruhl-desk.intel.com) ([10.124.221.121]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2025 11:45:42 -0700 From: "Michael J. Ruhl" To: platform-driver-x86@vger.kernel.org, intel-xe@lists.freedesktop.org, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, lucas.demarchi@intel.com, rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com Cc: "Michael J. Ruhl" Subject: [PATCH v7 11/12] platform/x86/intel/pmt: use a version struct Date: Wed, 9 Jul 2025 14:44:57 -0400 Message-ID: <20250709184458.298283-12-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250709184458.298283-1-michael.j.ruhl@intel.com> References: <20250709184458.298283-1-michael.j.ruhl@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" In preparation for supporting multiple crashlog versions, use a struct to keep bit offset info for the status and control bits. Reviewed-by: Ilpo Järvinen Signed-off-by: Michael J. Ruhl --- drivers/platform/x86/intel/pmt/crashlog.c | 92 ++++++++++++++++------- 1 file changed, 66 insertions(+), 26 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x86/intel/pmt/crashlog.c index 087b7110ddd2..91c7ff123e01 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -24,21 +24,6 @@ /* Crashlog discovery header types */ #define CRASH_TYPE_OOBMSM 1 -/* Control Flags */ -#define CRASHLOG_FLAG_DISABLE BIT(28) - -/* - * Bits 29 and 30 control the state of bit 31. - * - * Bit 29 will clear bit 31, if set, allowing a new crashlog to be captured. - * Bit 30 will immediately trigger a crashlog to be generated, setting bit 31. - * Bit 31 is the read-only status with a 1 indicating log is complete. - */ -#define CRASHLOG_FLAG_TRIGGER_CLEAR BIT(29) -#define CRASHLOG_FLAG_TRIGGER_EXECUTE BIT(30) -#define CRASHLOG_FLAG_TRIGGER_COMPLETE BIT(31) -#define CRASHLOG_FLAG_TRIGGER_MASK GENMASK(31, 28) - /* Crashlog Discovery Header */ #define CONTROL_OFFSET 0x0 #define GUID_OFFSET 0x4 @@ -50,10 +35,63 @@ /* size is in bytes */ #define GET_SIZE(v) ((v) * sizeof(u32)) +/* + * Type 1 Version 0 + * status and control registers are combined. + * + * Bits 29 and 30 control the state of bit 31. + * Bit 29 will clear bit 31, if set, allowing a new crashlog to be captured. + * Bit 30 will immediately trigger a crashlog to be generated, setting bit 31. + * Bit 31 is the read-only status with a 1 indicating log is complete. + */ +#define TYPE1_VER0_STATUS_OFFSET 0x00 +#define TYPE1_VER0_CONTROL_OFFSET 0x00 + +#define TYPE1_VER0_DISABLE BIT(28) +#define TYPE1_VER0_CLEAR BIT(29) +#define TYPE1_VER0_EXECUTE BIT(30) +#define TYPE1_VER0_COMPLETE BIT(31) +#define TYPE1_VER0_TRIGGER_MASK GENMASK(31, 28) + +/* After offset, order alphabetically, not bit ordered */ +struct crashlog_status { + u32 offset; + u32 cleared; + u32 complete; + u32 disabled; +}; + +struct crashlog_control { + u32 offset; + u32 trigger_mask; + u32 clear; + u32 disable; + u32 manual; +}; + +struct crashlog_info { + struct crashlog_status status; + struct crashlog_control control; +}; + +static const struct crashlog_info crashlog_type1_ver0 = { + .status.offset = TYPE1_VER0_STATUS_OFFSET, + .status.cleared = TYPE1_VER0_CLEAR, + .status.complete = TYPE1_VER0_COMPLETE, + .status.disabled = TYPE1_VER0_DISABLE, + + .control.offset = TYPE1_VER0_CONTROL_OFFSET, + .control.trigger_mask = TYPE1_VER0_TRIGGER_MASK, + .control.clear = TYPE1_VER0_CLEAR, + .control.disable = TYPE1_VER0_DISABLE, + .control.manual = TYPE1_VER0_EXECUTE, +}; + struct crashlog_entry { /* entry must be first member of struct */ struct intel_pmt_entry entry; struct mutex control_mutex; + const struct crashlog_info *info; }; struct pmt_crashlog_priv { @@ -68,24 +106,25 @@ struct pmt_crashlog_priv { /* Read, modify, write the control register, setting or clearing @bit based on @set */ static void pmt_crashlog_rmw(struct crashlog_entry *crashlog, u32 bit, bool set) { + const struct crashlog_control *control = &crashlog->info->control; struct intel_pmt_entry *entry = &crashlog->entry; - u32 reg = readl(entry->disc_table + CONTROL_OFFSET); + u32 reg = readl(entry->disc_table + control->offset); - reg &= ~CRASHLOG_FLAG_TRIGGER_MASK; + reg &= ~control->trigger_mask; if (set) reg |= bit; else reg &= ~bit; - writel(reg, entry->disc_table + CONTROL_OFFSET); + writel(reg, entry->disc_table + control->offset); } /* Read the status register and see if the specified @bit is set */ static bool pmt_crashlog_rc(struct crashlog_entry *crashlog, u32 bit) { - struct intel_pmt_entry *entry = &crashlog->entry; - u32 reg = readl(entry->disc_table + CONTROL_OFFSET); + const struct crashlog_status *status = &crashlog->info->status; + u32 reg = readl(crashlog->entry.disc_table + status->offset); return !!(reg & bit); } @@ -93,13 +132,13 @@ static bool pmt_crashlog_rc(struct crashlog_entry *crashlog, u32 bit) static bool pmt_crashlog_complete(struct crashlog_entry *crashlog) { /* return current value of the crashlog complete flag */ - return pmt_crashlog_rc(crashlog, CRASHLOG_FLAG_TRIGGER_COMPLETE); + return pmt_crashlog_rc(crashlog, crashlog->info->status.complete); } static bool pmt_crashlog_disabled(struct crashlog_entry *crashlog) { /* return current value of the crashlog disabled flag */ - return pmt_crashlog_rc(crashlog, CRASHLOG_FLAG_DISABLE); + return pmt_crashlog_rc(crashlog, crashlog->info->status.disabled); } static bool pmt_crashlog_supported(struct intel_pmt_entry *entry) @@ -120,17 +159,17 @@ static bool pmt_crashlog_supported(struct intel_pmt_entry *entry) static void pmt_crashlog_set_disable(struct crashlog_entry *crashlog, bool disable) { - pmt_crashlog_rmw(crashlog, CRASHLOG_FLAG_DISABLE, disable); + pmt_crashlog_rmw(crashlog, crashlog->info->control.disable, disable); } static void pmt_crashlog_set_clear(struct crashlog_entry *crashlog) { - pmt_crashlog_rmw(crashlog, CRASHLOG_FLAG_TRIGGER_CLEAR, true); + pmt_crashlog_rmw(crashlog, crashlog->info->control.clear, true); } static void pmt_crashlog_set_execute(struct crashlog_entry *crashlog) { - pmt_crashlog_rmw(crashlog, CRASHLOG_FLAG_TRIGGER_EXECUTE, true); + pmt_crashlog_rmw(crashlog, crashlog->info->control.manual, true); } /* @@ -234,9 +273,10 @@ static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, if (!pmt_crashlog_supported(entry)) return 1; - /* initialize control mutex */ + /* initialize the crashlog struct */ crashlog = container_of(entry, struct crashlog_entry, entry); mutex_init(&crashlog->control_mutex); + crashlog->info = &crashlog_type1_ver0; header->access_type = GET_ACCESS(readl(disc_table)); header->guid = readl(disc_table + GUID_OFFSET); -- 2.50.0