From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEBABC83F26 for ; Mon, 28 Jul 2025 18:29:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FAE810E56E; Mon, 28 Jul 2025 18:29:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mKFdAWgv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id D0E7810E0CE for ; Mon, 28 Jul 2025 18:29:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1753727380; x=1785263380; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=eAOxmb2iVMWRqmh/TmtAvfA+gW4DTn18FC0gdhljrF8=; b=mKFdAWgvXPnMtmHVJHOwZLr+N397HQzNv5KfNXZBLmqV8FEefigMcwOb 3ENOJkF3L6kaJwggQ1Vm/KEjVeiAaebJ3wUfsv+zcEtS6pNmeQvXlvYK8 BMxxV135wGRFdoSoJ7WIy/y5PfHDA44+oBN+GAn8C8EHKECDJwYN3V2NK QM71aYK9CXTV5jBmmhqlyIMd+jz4m+IG6acF9ofb/PXgfFEizVI8Jn+nN EHf8qaJ5K7tEX+tCiGhO+hTMcnN7i/6WK4soZ67Bg6cU5GXDDCWFXoSXi GLy4CmiV+BcNWe/i6EBSi4iCL4y02zdaAr6p13K4JkjFp4tbwedRYpOFv Q==; X-CSE-ConnectionGUID: 0W6YTLKUQBK8u+O8VDJtaw== X-CSE-MsgGUID: UVOgu7RIS42IvpRuT1YsmA== X-IronPort-AV: E=McAfee;i="6800,10657,11505"; a="67067692" X-IronPort-AV: E=Sophos;i="6.16,339,1744095600"; d="scan'208";a="67067692" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2025 11:29:40 -0700 X-CSE-ConnectionGUID: DpA34yHORYygvDkCfSdOyw== X-CSE-MsgGUID: YdNi7baZT5uI9xvMs5iKaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,339,1744095600"; d="scan'208";a="166969359" Received: from inaky-mobl1.amr.corp.intel.com (HELO gjsousa-mobl2.amr.corp.intel.com) ([10.125.109.81]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2025 11:29:39 -0700 From: Gustavo Sousa Date: Mon, 28 Jul 2025 15:29:06 -0300 Subject: [PATCH v2 2/2] drm/xe: Use for_each_gt to define gt_count MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250728-gt_count-improvements-v2-2-78841ce8a81c@intel.com> References: <20250728-gt_count-improvements-v2-0-78841ce8a81c@intel.com> In-Reply-To: <20250728-gt_count-improvements-v2-0-78841ce8a81c@intel.com> To: intel-xe@lists.freedesktop.org Cc: Jonathan Cavitt , Gustavo Sousa X-Mailer: b4 0.15-dev X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" We are currently bumping gt_count as we define GTs for each tile. While that works with our current code, there are reasons to improve that: * That section of the code is dedicated to define each tile's set of GTs and their respective info. The gt_count can be seen as a device level property. While it is fair to bump it as we define each GT, we can also focus on the GT themselves and count after we are done with the definitions. * More *importantly*, gt_count should reflect the number of GTs that we would get when looping over them with for_each_gt(). Bumping gt_count the way we are currently doing makes that value not really connected to for_each_gt(). This could bite us in the future if in the loop gets extra checks that are not accounted for in each existing "gt_count++". As such, let's use for_each_gt() and extract the calculation of gt_count into a separate block, just after we define the set of GTs for each tile. Reviewed-by: Jonathan Cavitt Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/xe/xe_pci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 0d7073a04bb2..12de65756599 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -734,7 +734,6 @@ static int xe_info_init(struct xe_device *xe, gt->info.id = tile->id * xe->info.max_gt_per_tile; gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; gt->info.engine_mask = graphics_desc->hw_engine_mask; - xe->info.gt_count++; err = xe_tile_alloc_vram(tile); if (err) @@ -759,9 +758,15 @@ static int xe_info_init(struct xe_device *xe, gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; gt->info.engine_mask = media_desc->hw_engine_mask; - xe->info.gt_count++; } + /* + * Now that we have tiles and GTs defined, let's loop over valid GTs + * in order to define gt_count. + */ + for_each_gt(gt, xe, id) + xe->info.gt_count++; + return 0; } -- 2.50.1