* [PATCH 01/10] drm/xe: Handle errors from various components.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 9:08 ` Michal Wajdeczko
2025-07-30 19:59 ` Rodrigo Vivi
2025-07-30 5:48 ` [PATCH 02/10] drm/xe: Add new helpers to log hardware errrors Aravind Iddamsetty
` (12 subsequent siblings)
13 siblings, 2 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
The GFX device reports two classes of errors: uncorrectable and
correctable. Depending on the severity uncorrectable errors are
further classified as non fatal and fatal. Driver will only handle
logging of errors and updating counters from various components within
the graphics device. Anything more will be handled at system level.
Correctable and NonFatal errors are reported as interrupts, bits in
the Master Interrupt Register will be used to convey the class of error.
Determine source of error (IP block) by reading the Device Error Source
Register (RW1C) that corresponds to the class of error being serviced
Fatal errors are reported as PCIe errors. When a PCIe error is asserted,
the OS will perform a device warm reset which causes the driver to
reload. The error registers are sticky and the values are maintained
through a warm reset. We read these registers during the boot flow of the
driver and increment the respective error counters.
Bspec: 50875, 53073, 53074, 53075, 53076
v6
- Limit the implementation to DG2 and PVC.
- Limit the tile level logging to only PVC.
- Use xarray instead of array for error counters.
- Squash the fatal error reporting patch with this patch.
- use drm_dbg instead of drm_info to dump register values.
- use XE_HW_ERR_UNSPEC for error which are reported by leaf registers.
- use source_typeoferror_errorname convention for enum and error loging.
- Clean unused enums and there are no display supported ras error,
categorize them as unknown.
- Dont make xe_assign_hw_err_regs static.
- Use err_name_index_pair instead of err_msg_cntr_pair.(Aravind)
v7
- Ci fix
v8
- Avoid unnecessary write if reg is empty incase of DG2.
v9
- For reg being blank print error for DG2 too.
- Maintain order of headers.
- Make XE_HW_ERR_UNSPEC 0. (Aravind)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
drivers/gpu/drm/xe/regs/xe_regs.h | 3 +
drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 13 +
drivers/gpu/drm/xe/xe_device.c | 13 +
drivers/gpu/drm/xe/xe_device_types.h | 10 +
drivers/gpu/drm/xe/xe_hw_error.c | 258 +++++++++++++++++++
drivers/gpu/drm/xe/xe_hw_error.h | 50 ++++
drivers/gpu/drm/xe/xe_irq.c | 1 +
drivers/gpu/drm/xe/xe_tile.c | 2 +
10 files changed, 352 insertions(+)
create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 42c6ca5b3f76..80eecd35e807 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -82,6 +82,7 @@ xe-y += xe_bb.o \
xe_hw_engine.o \
xe_hw_engine_class_sysfs.o \
xe_hw_engine_group.o \
+ xe_hw_error.o \
xe_hw_fence.o \
xe_irq.o \
xe_lrc.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 13635e4331d4..086ec7584b1a 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -18,6 +18,7 @@
#define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF)
#define MASTER_IRQ REG_BIT(31)
#define GU_MISC_IRQ REG_BIT(29)
+#define XE_ERROR_IRQ(x) REG_BIT(26 + (x))
#define DISPLAY_IRQ REG_BIT(16)
#define I2C_IRQ REG_BIT(12)
#define GT_DW_IRQ(x) REG_BIT(x)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 1926b4044314..00900d3821f7 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -9,6 +9,9 @@
#define SOC_BASE 0x280000
+#define DEV_PCIEERR_STATUS XE_REG(0x100180)
+#define DEV_PCIEERR_IS_FATAL(x) REG_BIT(x * 4 + 2)
+
#define GU_CNTL_PROTECTED XE_REG(0x10100C)
#define DRIVERINT_FLR_DIS REG_BIT(31)
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
new file mode 100644
index 000000000000..ba5480fb2789
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_TILE_ERROR_REGS_H_
+#define XE_TILE_ERROR_REGS_H_
+
+#define _DEV_ERR_STAT_NONFATAL 0x100178
+#define _DEV_ERR_STAT_CORRECTABLE 0x10017c
+#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
+ _DEV_ERR_STAT_CORRECTABLE, \
+ _DEV_ERR_STAT_NONFATAL))
+#endif
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index d04a0ae018e6..e0625fa5b1ca 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -875,6 +875,8 @@ int xe_device_probe(struct xe_device *xe)
return err;
}
+ xe_init_hw_errors(xe);
+
err = xe_irq_install(xe);
if (err)
return err;
@@ -952,6 +954,15 @@ int xe_device_probe(struct xe_device *xe)
return err;
}
+static void xe_hw_error_fini(struct xe_device *xe)
+{
+ struct xe_tile *tile;
+ int i;
+
+ for_each_tile(tile, xe, i)
+ xa_destroy(&tile->errors.hw_error);
+}
+
void xe_device_remove(struct xe_device *xe)
{
xe_display_unregister(xe);
@@ -961,6 +972,8 @@ void xe_device_remove(struct xe_device *xe)
drm_dev_unplug(&xe->drm);
xe_bo_pci_dev_remove_all(xe);
+
+ xe_hw_error_fini(xe);
}
void xe_device_shutdown(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 38c8329b4d2c..233c2751d09f 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -14,6 +14,7 @@
#include "xe_devcoredump_types.h"
#include "xe_heci_gsc.h"
+#include "xe_hw_error.h"
#include "xe_lmtt_types.h"
#include "xe_memirq_types.h"
#include "xe_oa_types.h"
@@ -206,6 +207,11 @@ struct xe_tile {
/** @debugfs: debugfs directory associated with this tile */
struct dentry *debugfs;
+
+ /** @errors: count of hardware errors reported for the tile */
+ struct tile_hw_errors {
+ struct xarray hw_error;
+ } errors;
};
/**
@@ -575,6 +581,10 @@ struct xe_device {
*/
atomic64_t global_total_pages;
#endif
+ /** @hw_err_regs: list of hw error regs*/
+ struct hardware_errors_regs {
+ const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
+ } hw_err_regs;
/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
new file mode 100644
index 000000000000..84830ad81813
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "xe_hw_error.h"
+
+#include "regs/xe_regs.h"
+#include "regs/xe_irq_regs.h"
+#include "regs/xe_tile_error_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+
+static const char *
+hardware_error_type_to_str(const enum hardware_error hw_err)
+{
+ switch (hw_err) {
+ case HARDWARE_ERROR_CORRECTABLE:
+ return "CORRECTABLE";
+ case HARDWARE_ERROR_NONFATAL:
+ return "NONFATAL";
+ case HARDWARE_ERROR_FATAL:
+ return "FATAL";
+ default:
+ return "UNKNOWN";
+ }
+}
+
+static const struct err_name_index_pair dg2_err_stat_fatal_reg[] = {
+ [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
+ [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
+ [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [12] = {"SGUNIT", XE_HW_ERR_TILE_FATAL_SGUNIT},
+ [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
+ [17 ... 31] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair dg2_err_stat_nonfatal_reg[] = {
+ [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
+ [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
+ [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [12] = {"SGUNIT", XE_HW_ERR_TILE_NONFATAL_SGUNIT},
+ [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
+ [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [20] = {"MERT", XE_HW_ERR_TILE_NONFATAL_MERT},
+ [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair dg2_err_stat_correctable_reg[] = {
+ [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
+ [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+ [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+ [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
+ [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+ [12] = {"SGUNIT", XE_HW_ERR_TILE_CORR_SGUNIT},
+ [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+ [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
+ [17 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_fatal_reg[] = {
+ [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
+ [1] = {"SGGI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGGI},
+ [2 ... 7] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
+ [9] = {"SGLI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGLI},
+ [10 ... 12] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [13] = {"SGCI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGCI},
+ [14 ... 15] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [16] = {"SOC ERROR", XE_HW_ERR_TILE_UNSPEC},
+ [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+ [20] = {"MERT Cmd Parity", XE_HW_ERR_TILE_FATAL_MERT},
+ [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_nonfatal_reg[] = {
+ [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
+ [1] = {"SGGI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGGI},
+ [2 ... 7] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
+ [9] = {"SGLI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGLI},
+ [10 ... 12] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [13] = {"SGCI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGCI},
+ [14 ... 15] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
+ [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+ [20] = {"MERT Data Parity", XE_HW_ERR_TILE_NONFATAL_MERT},
+ [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
+ [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
+ [1 ... 7] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+ [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
+ [9 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
+};
+
+static void xe_assign_hw_err_regs(struct xe_device *xe)
+{
+ const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
+
+ /* Error reporting is supported only for DG2 and PVC currently. */
+ if (xe->info.platform == XE_DG2) {
+ dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
+ dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
+ dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
+ }
+
+ if (xe->info.platform == XE_PVC) {
+ dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
+ dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
+ dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
+ }
+}
+
+static bool xe_platform_has_ras(struct xe_device *xe)
+{
+ if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2)
+ return true;
+
+ return false;
+}
+
+static void
+xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
+{
+ unsigned long flags;
+ void *entry;
+
+ entry = xa_load(hw_error, index);
+ entry = xa_mk_value(xa_to_value(entry) + 1);
+
+ xa_lock_irqsave(hw_error, flags);
+ if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
+ drm_err_ratelimited(drm,
+ HW_ERR "Error reported by index %ld is lost\n", index);
+ xa_unlock_irqrestore(hw_error, flags);
+}
+
+static void
+xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+ const char *hw_err_str = hardware_error_type_to_str(hw_err);
+ const struct hardware_errors_regs *err_regs;
+ const struct err_name_index_pair *errstat;
+ unsigned long errsrc;
+ unsigned long flags;
+ const char *name;
+ u32 indx;
+ u32 errbit;
+
+ if (!xe_platform_has_ras(tile_to_xe(tile)))
+ return;
+
+ spin_lock_irqsave(&tile_to_xe(tile)->irq.lock, flags);
+ err_regs = &tile_to_xe(tile)->hw_err_regs;
+ errstat = err_regs->dev_err_stat[hw_err];
+ errsrc = xe_mmio_read32(&tile->mmio, DEV_ERR_STAT_REG(hw_err));
+ if (!errsrc) {
+ drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+ "TILE%d reported DEV_ERR_STAT_REG_%s blank!\n",
+ tile->id, hw_err_str);
+ goto unlock;
+ }
+
+ if (tile_to_xe(tile)->info.platform != XE_DG2)
+ drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+ "TILE%d reported DEV_ERR_STAT_REG_%s=0x%08lx\n",
+ tile->id, hw_err_str, errsrc);
+
+ for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
+ name = errstat[errbit].name;
+ indx = errstat[errbit].index;
+
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE &&
+ tile_to_xe(tile)->info.platform != XE_DG2)
+ drm_warn(&tile_to_xe(tile)->drm,
+ HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
+ tile->id, name, hw_err_str, errbit);
+
+ else if (tile_to_xe(tile)->info.platform != XE_DG2)
+ drm_err_ratelimited(&tile_to_xe(tile)->drm,
+ HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
+ tile->id, name, hw_err_str, errbit);
+
+ if (indx != XE_HW_ERR_TILE_UNSPEC)
+ xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
+ &tile->errors.hw_error, indx);
+ }
+
+ xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
+unlock:
+ spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
+}
+
+/*
+ * XE Platforms adds three Error bits to the Master Interrupt
+ * Register to support error handling. These three bits are
+ * used to convey the class of error:
+ * FATAL, NONFATAL, or CORRECTABLE.
+ *
+ * To process an interrupt:
+ * Determine source of error (IP block) by reading
+ * the Device Error Source Register (RW1C) that
+ * corresponds to the class of error being serviced
+ * and log the error.
+ */
+void
+xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
+{
+ enum hardware_error hw_err;
+
+ for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
+ if (master_ctl & XE_ERROR_IRQ(hw_err))
+ xe_hw_error_source_handler(tile, hw_err);
+ }
+}
+
+/*
+ * xe_process_hw_errors - checks for the occurrence of HW errors
+ *
+ * Fatal will result in a card warm reset and driver will be reloaded.
+ * This checks for the HW Errors that might have occurred in the
+ * previous boot of the driver.
+ */
+static void xe_process_hw_errors(struct xe_device *xe)
+{
+ struct xe_mmio *root_mmio = xe_root_tile_mmio(xe);
+
+ u32 dev_pcieerr_status, master_ctl;
+ struct xe_tile *tile;
+ int i;
+
+ dev_pcieerr_status = xe_mmio_read32(root_mmio, DEV_PCIEERR_STATUS);
+
+ for_each_tile(tile, xe, i) {
+ if (dev_pcieerr_status & DEV_PCIEERR_IS_FATAL(i))
+ xe_hw_error_source_handler(tile, HARDWARE_ERROR_FATAL);
+
+ master_ctl = xe_mmio_read32(&tile->mmio, GFX_MSTR_IRQ);
+ xe_hw_error_irq_handler(tile, master_ctl);
+ xe_mmio_write32(&tile->mmio, GFX_MSTR_IRQ, master_ctl);
+ }
+ if (dev_pcieerr_status)
+ xe_mmio_write32(root_mmio, DEV_PCIEERR_STATUS, dev_pcieerr_status);
+}
+
+void xe_init_hw_errors(struct xe_device *xe)
+{
+ xe_assign_hw_err_regs(xe);
+ xe_process_hw_errors(xe);
+}
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
new file mode 100644
index 000000000000..398e2a7f2ac6
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_HW_ERRORS_H_
+#define XE_HW_ERRORS_H_
+
+#include <linux/stddef.h>
+#include <linux/types.h>
+
+#define XE_RAS_REG_SIZE 32
+
+/* Error categories reported by hardware */
+enum hardware_error {
+ HARDWARE_ERROR_CORRECTABLE = 0,
+ HARDWARE_ERROR_NONFATAL = 1,
+ HARDWARE_ERROR_FATAL = 2,
+ HARDWARE_ERROR_MAX,
+};
+
+/* Count of Correctable and Uncorrectable errors reported on tile */
+enum xe_tile_hw_errors {
+ XE_HW_ERR_TILE_UNSPEC = 0,
+ XE_HW_ERR_TILE_FATAL_SGGI,
+ XE_HW_ERR_TILE_FATAL_SGLI,
+ XE_HW_ERR_TILE_FATAL_SGUNIT,
+ XE_HW_ERR_TILE_FATAL_SGCI,
+ XE_HW_ERR_TILE_FATAL_MERT,
+ XE_HW_ERR_TILE_FATAL_UNKNOWN,
+ XE_HW_ERR_TILE_NONFATAL_SGGI,
+ XE_HW_ERR_TILE_NONFATAL_SGLI,
+ XE_HW_ERR_TILE_NONFATAL_SGUNIT,
+ XE_HW_ERR_TILE_NONFATAL_SGCI,
+ XE_HW_ERR_TILE_NONFATAL_MERT,
+ XE_HW_ERR_TILE_NONFATAL_UNKNOWN,
+ XE_HW_ERR_TILE_CORR_SGUNIT,
+ XE_HW_ERR_TILE_CORR_UNKNOWN,
+};
+
+struct err_name_index_pair {
+ const char *name;
+ const u32 index;
+};
+
+struct xe_device;
+struct xe_tile;
+
+void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
+void xe_init_hw_errors(struct xe_device *xe);
+#endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 5df5b8c2a3e4..1e9cfb8bb85d 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -468,6 +468,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
gt_irq_handler(tile, master_ctl, intr_dw, identity);
+ xe_hw_error_irq_handler(tile, master_ctl);
/*
* Display interrupts (including display backlight operations
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index d49ba3401963..b00c517e5559 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -91,6 +91,8 @@
*/
static int xe_tile_alloc(struct xe_tile *tile)
{
+ xa_init(&tile->errors.hw_error);
+
tile->mem.ggtt = xe_ggtt_alloc(tile);
if (!tile->mem.ggtt)
return -ENOMEM;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 01/10] drm/xe: Handle errors from various components.
2025-07-30 5:48 ` [PATCH 01/10] drm/xe: Handle errors from various components Aravind Iddamsetty
@ 2025-07-30 9:08 ` Michal Wajdeczko
2025-07-30 19:59 ` Rodrigo Vivi
1 sibling, 0 replies; 18+ messages in thread
From: Michal Wajdeczko @ 2025-07-30 9:08 UTC (permalink / raw)
To: Aravind Iddamsetty, intel-xe
Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
On 7/30/2025 7:48 AM, Aravind Iddamsetty wrote:
> From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
> The GFX device reports two classes of errors: uncorrectable and
> correctable. Depending on the severity uncorrectable errors are
> further classified as non fatal and fatal. Driver will only handle
> logging of errors and updating counters from various components within
> the graphics device. Anything more will be handled at system level.
>
> Correctable and NonFatal errors are reported as interrupts, bits in
> the Master Interrupt Register will be used to convey the class of error.
> Determine source of error (IP block) by reading the Device Error Source
> Register (RW1C) that corresponds to the class of error being serviced
>
> Fatal errors are reported as PCIe errors. When a PCIe error is asserted,
> the OS will perform a device warm reset which causes the driver to
> reload. The error registers are sticky and the values are maintained
> through a warm reset. We read these registers during the boot flow of the
> driver and increment the respective error counters.
>
> Bspec: 50875, 53073, 53074, 53075, 53076
>
> v6
> - Limit the implementation to DG2 and PVC.
> - Limit the tile level logging to only PVC.
> - Use xarray instead of array for error counters.
> - Squash the fatal error reporting patch with this patch.
> - use drm_dbg instead of drm_info to dump register values.
> - use XE_HW_ERR_UNSPEC for error which are reported by leaf registers.
> - use source_typeoferror_errorname convention for enum and error loging.
> - Clean unused enums and there are no display supported ras error,
> categorize them as unknown.
> - Dont make xe_assign_hw_err_regs static.
> - Use err_name_index_pair instead of err_msg_cntr_pair.(Aravind)
>
> v7
> - Ci fix
>
> v8
> - Avoid unnecessary write if reg is empty incase of DG2.
>
> v9
> - For reg being blank print error for DG2 too.
> - Maintain order of headers.
> - Make XE_HW_ERR_UNSPEC 0. (Aravind)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> drivers/gpu/drm/xe/regs/xe_regs.h | 3 +
> drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 13 +
> drivers/gpu/drm/xe/xe_device.c | 13 +
> drivers/gpu/drm/xe/xe_device_types.h | 10 +
> drivers/gpu/drm/xe/xe_hw_error.c | 258 +++++++++++++++++++
> drivers/gpu/drm/xe/xe_hw_error.h | 50 ++++
> drivers/gpu/drm/xe/xe_irq.c | 1 +
> drivers/gpu/drm/xe/xe_tile.c | 2 +
> 10 files changed, 352 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
> create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 42c6ca5b3f76..80eecd35e807 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -82,6 +82,7 @@ xe-y += xe_bb.o \
> xe_hw_engine.o \
> xe_hw_engine_class_sysfs.o \
> xe_hw_engine_group.o \
> + xe_hw_error.o \
> xe_hw_fence.o \
> xe_irq.o \
> xe_lrc.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 13635e4331d4..086ec7584b1a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -18,6 +18,7 @@
> #define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF)
> #define MASTER_IRQ REG_BIT(31)
> #define GU_MISC_IRQ REG_BIT(29)
> +#define XE_ERROR_IRQ(x) REG_BIT(26 + (x))
> #define DISPLAY_IRQ REG_BIT(16)
> #define I2C_IRQ REG_BIT(12)
> #define GT_DW_IRQ(x) REG_BIT(x)
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 1926b4044314..00900d3821f7 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -9,6 +9,9 @@
>
> #define SOC_BASE 0x280000
>
> +#define DEV_PCIEERR_STATUS XE_REG(0x100180)
> +#define DEV_PCIEERR_IS_FATAL(x) REG_BIT(x * 4 + 2)
> +
> #define GU_CNTL_PROTECTED XE_REG(0x10100C)
> #define DRIVERINT_FLR_DIS REG_BIT(31)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> new file mode 100644
> index 000000000000..ba5480fb2789
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef XE_TILE_ERROR_REGS_H_
> +#define XE_TILE_ERROR_REGS_H_
> +
> +#define _DEV_ERR_STAT_NONFATAL 0x100178
> +#define _DEV_ERR_STAT_CORRECTABLE 0x10017c
> +#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
> + _DEV_ERR_STAT_CORRECTABLE, \
> + _DEV_ERR_STAT_NONFATAL))
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index d04a0ae018e6..e0625fa5b1ca 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -875,6 +875,8 @@ int xe_device_probe(struct xe_device *xe)
> return err;
> }
>
> + xe_init_hw_errors(xe);
> +
> err = xe_irq_install(xe);
> if (err)
> return err;
> @@ -952,6 +954,15 @@ int xe_device_probe(struct xe_device *xe)
> return err;
> }
>
> +static void xe_hw_error_fini(struct xe_device *xe)
> +{
> + struct xe_tile *tile;
> + int i;
> +
> + for_each_tile(tile, xe, i)
> + xa_destroy(&tile->errors.hw_error);
> +}
> +
> void xe_device_remove(struct xe_device *xe)
> {
> xe_display_unregister(xe);
> @@ -961,6 +972,8 @@ void xe_device_remove(struct xe_device *xe)
> drm_dev_unplug(&xe->drm);
>
> xe_bo_pci_dev_remove_all(xe);
> +
> + xe_hw_error_fini(xe);
this should be a devm action registered by xe_init_hw_errors()
> }
>
> void xe_device_shutdown(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 38c8329b4d2c..233c2751d09f 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -14,6 +14,7 @@
>
> #include "xe_devcoredump_types.h"
> #include "xe_heci_gsc.h"
> +#include "xe_hw_error.h"
> #include "xe_lmtt_types.h"
> #include "xe_memirq_types.h"
> #include "xe_oa_types.h"
> @@ -206,6 +207,11 @@ struct xe_tile {
>
> /** @debugfs: debugfs directory associated with this tile */
> struct dentry *debugfs;
> +
> + /** @errors: count of hardware errors reported for the tile */
> + struct tile_hw_errors {
> + struct xarray hw_error;
> + } errors;
> };
>
> /**
> @@ -575,6 +581,10 @@ struct xe_device {
> */
> atomic64_t global_total_pages;
> #endif
> + /** @hw_err_regs: list of hw error regs*/
> + struct hardware_errors_regs {
> + const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
> + } hw_err_regs;
>
> /* private: */
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> new file mode 100644
> index 000000000000..84830ad81813
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -0,0 +1,258 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
2025 ? everywhere
> + */
> +
> +#include "xe_hw_error.h"
> +
> +#include "regs/xe_regs.h"
> +#include "regs/xe_irq_regs.h"
> +#include "regs/xe_tile_error_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +
> +static const char *
> +hardware_error_type_to_str(const enum hardware_error hw_err)
> +{
> + switch (hw_err) {
> + case HARDWARE_ERROR_CORRECTABLE:
> + return "CORRECTABLE";
> + case HARDWARE_ERROR_NONFATAL:
> + return "NONFATAL";
> + case HARDWARE_ERROR_FATAL:
> + return "FATAL";
> + default:
> + return "UNKNOWN";
> + }
> +}
> +
> +static const struct err_name_index_pair dg2_err_stat_fatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [12] = {"SGUNIT", XE_HW_ERR_TILE_FATAL_SGUNIT},
> + [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 31] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair dg2_err_stat_nonfatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [12] = {"SGUNIT", XE_HW_ERR_TILE_NONFATAL_SGUNIT},
> + [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [20] = {"MERT", XE_HW_ERR_TILE_NONFATAL_MERT},
> + [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair dg2_err_stat_correctable_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [12] = {"SGUNIT", XE_HW_ERR_TILE_CORR_SGUNIT},
> + [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_fatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1] = {"SGGI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGGI},
> + [2 ... 7] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9] = {"SGLI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGLI},
> + [10 ... 12] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [13] = {"SGCI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGCI},
> + [14 ... 15] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [16] = {"SOC ERROR", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [20] = {"MERT Cmd Parity", XE_HW_ERR_TILE_FATAL_MERT},
> + [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_nonfatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1] = {"SGGI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGGI},
> + [2 ... 7] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9] = {"SGLI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGLI},
> + [10 ... 12] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [13] = {"SGCI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGCI},
> + [14 ... 15] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [20] = {"MERT Data Parity", XE_HW_ERR_TILE_NONFATAL_MERT},
> + [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 7] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> +};
> +
> +static void xe_assign_hw_err_regs(struct xe_device *xe)
> +{
> + const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> +
> + /* Error reporting is supported only for DG2 and PVC currently. */
> + if (xe->info.platform == XE_DG2) {
> + dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
> + dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
> + dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
> + }
> +
else
> + if (xe->info.platform == XE_PVC) {
> + dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
> + dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
> + dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
> + }
and I guess the 'if' ladder shall start with newest platforms first
> +}
> +
> +static bool xe_platform_has_ras(struct xe_device *xe)
> +{
> + if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2)
> + return true;
> +
> + return false;
this could be one line
return xe->info.platform == XE_PVC || xe->info.platform == XE_DG2;
but likely it should start with
if (IS_SRIOV_VF(xe))
return false;
> +}
> +
> +static void
> +xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
> +{
> + unsigned long flags;
> + void *entry;
> +
> + entry = xa_load(hw_error, index);
> + entry = xa_mk_value(xa_to_value(entry) + 1);
> +
> + xa_lock_irqsave(hw_error, flags);
> + if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
> + drm_err_ratelimited(drm,
> + HW_ERR "Error reported by index %ld is lost\n", index);
> + xa_unlock_irqrestore(hw_error, flags);
> +}
> +
> +static void
> +xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
> +{
> + const char *hw_err_str = hardware_error_type_to_str(hw_err);
> + const struct hardware_errors_regs *err_regs;
> + const struct err_name_index_pair *errstat;
> + unsigned long errsrc;
> + unsigned long flags;
> + const char *name;
> + u32 indx;
> + u32 errbit;
> +
> + if (!xe_platform_has_ras(tile_to_xe(tile)))
> + return;
> +
> + spin_lock_irqsave(&tile_to_xe(tile)->irq.lock, flags);
> + err_regs = &tile_to_xe(tile)->hw_err_regs;
> + errstat = err_regs->dev_err_stat[hw_err];
> + errsrc = xe_mmio_read32(&tile->mmio, DEV_ERR_STAT_REG(hw_err));
> + if (!errsrc) {
> + drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> + "TILE%d reported DEV_ERR_STAT_REG_%s blank!\n",
> + tile->id, hw_err_str);
> + goto unlock;
> + }
> +
> + if (tile_to_xe(tile)->info.platform != XE_DG2)
> + drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
> + "TILE%d reported DEV_ERR_STAT_REG_%s=0x%08lx\n",
> + tile->id, hw_err_str, errsrc);
> +
> + for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
> + name = errstat[errbit].name;
> + indx = errstat[errbit].index;
> +
> + if (hw_err == HARDWARE_ERROR_CORRECTABLE &&
> + tile_to_xe(tile)->info.platform != XE_DG2)
> + drm_warn(&tile_to_xe(tile)->drm,
> + HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
> + tile->id, name, hw_err_str, errbit);
> +
> + else if (tile_to_xe(tile)->info.platform != XE_DG2)
> + drm_err_ratelimited(&tile_to_xe(tile)->drm,
> + HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
> + tile->id, name, hw_err_str, errbit);
> +
> + if (indx != XE_HW_ERR_TILE_UNSPEC)
> + xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
> + &tile->errors.hw_error, indx);
> + }
> +
> + xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
> +unlock:
> + spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
> +}
> +
> +/*
> + * XE Platforms adds three Error bits to the Master Interrupt
> + * Register to support error handling. These three bits are
> + * used to convey the class of error:
> + * FATAL, NONFATAL, or CORRECTABLE.
> + *
> + * To process an interrupt:
> + * Determine source of error (IP block) by reading
> + * the Device Error Source Register (RW1C) that
> + * corresponds to the class of error being serviced
> + * and log the error.
> + */
> +void
> +xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
> +{
> + enum hardware_error hw_err;
> +
> + for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
> + if (master_ctl & XE_ERROR_IRQ(hw_err))
> + xe_hw_error_source_handler(tile, hw_err);
> + }
> +}
> +
> +/*
> + * xe_process_hw_errors - checks for the occurrence of HW errors
> + *
> + * Fatal will result in a card warm reset and driver will be reloaded.
> + * This checks for the HW Errors that might have occurred in the
> + * previous boot of the driver.
> + */
> +static void xe_process_hw_errors(struct xe_device *xe)
> +{
> + struct xe_mmio *root_mmio = xe_root_tile_mmio(xe);
> +
> + u32 dev_pcieerr_status, master_ctl;
> + struct xe_tile *tile;
> + int i;
> +
> + dev_pcieerr_status = xe_mmio_read32(root_mmio, DEV_PCIEERR_STATUS);
> +
> + for_each_tile(tile, xe, i) {
> + if (dev_pcieerr_status & DEV_PCIEERR_IS_FATAL(i))
> + xe_hw_error_source_handler(tile, HARDWARE_ERROR_FATAL);
> +
> + master_ctl = xe_mmio_read32(&tile->mmio, GFX_MSTR_IRQ);
> + xe_hw_error_irq_handler(tile, master_ctl);
> + xe_mmio_write32(&tile->mmio, GFX_MSTR_IRQ, master_ctl);
> + }
> + if (dev_pcieerr_status)
> + xe_mmio_write32(root_mmio, DEV_PCIEERR_STATUS, dev_pcieerr_status);
> +}
> +
missing kernel-doc for public function
> +void xe_init_hw_errors(struct xe_device *xe)
> +{
shouldn't you check xe_platform_has_ras() here?
> + xe_assign_hw_err_regs(xe);
> + xe_process_hw_errors(xe);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> new file mode 100644
> index 000000000000..398e2a7f2ac6
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef XE_HW_ERRORS_H_
> +#define XE_HW_ERRORS_H_
> +
> +#include <linux/stddef.h>
> +#include <linux/types.h>
> +
> +#define XE_RAS_REG_SIZE 32
> +
> +/* Error categories reported by hardware */
> +enum hardware_error {
> + HARDWARE_ERROR_CORRECTABLE = 0,
> + HARDWARE_ERROR_NONFATAL = 1,
> + HARDWARE_ERROR_FATAL = 2,
> + HARDWARE_ERROR_MAX,
> +};
> +
> +/* Count of Correctable and Uncorrectable errors reported on tile */
> +enum xe_tile_hw_errors {
> + XE_HW_ERR_TILE_UNSPEC = 0,
> + XE_HW_ERR_TILE_FATAL_SGGI,
> + XE_HW_ERR_TILE_FATAL_SGLI,
> + XE_HW_ERR_TILE_FATAL_SGUNIT,
> + XE_HW_ERR_TILE_FATAL_SGCI,
> + XE_HW_ERR_TILE_FATAL_MERT,
> + XE_HW_ERR_TILE_FATAL_UNKNOWN,
> + XE_HW_ERR_TILE_NONFATAL_SGGI,
> + XE_HW_ERR_TILE_NONFATAL_SGLI,
> + XE_HW_ERR_TILE_NONFATAL_SGUNIT,
> + XE_HW_ERR_TILE_NONFATAL_SGCI,
> + XE_HW_ERR_TILE_NONFATAL_MERT,
> + XE_HW_ERR_TILE_NONFATAL_UNKNOWN,
> + XE_HW_ERR_TILE_CORR_SGUNIT,
> + XE_HW_ERR_TILE_CORR_UNKNOWN,
> +};
> +
> +struct err_name_index_pair {
> + const char *name;
> + const u32 index;
> +};
shouldn't above defs be in xe_hw_error_types.h ?
> +
> +struct xe_device;
> +struct xe_tile;
> +
> +void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
> +void xe_init_hw_errors(struct xe_device *xe);
naming seems wrong:
void xe_hw_error_init(struct xe_device *xe);
void xe_hw_error_irq_handler(struct xe_tile *tile, u32 master_ctl);
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 5df5b8c2a3e4..1e9cfb8bb85d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -468,6 +468,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
>
> gt_irq_handler(tile, master_ctl, intr_dw, identity);
> + xe_hw_error_irq_handler(tile, master_ctl);
>
> /*
> * Display interrupts (including display backlight operations
> diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
> index d49ba3401963..b00c517e5559 100644
> --- a/drivers/gpu/drm/xe/xe_tile.c
> +++ b/drivers/gpu/drm/xe/xe_tile.c
> @@ -91,6 +91,8 @@
> */
> static int xe_tile_alloc(struct xe_tile *tile)
> {
> + xa_init(&tile->errors.hw_error);
shouldn't this be part of xe_init_hw_errors() ?
> +
> tile->mem.ggtt = xe_ggtt_alloc(tile);
> if (!tile->mem.ggtt)
> return -ENOMEM;
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 01/10] drm/xe: Handle errors from various components.
2025-07-30 5:48 ` [PATCH 01/10] drm/xe: Handle errors from various components Aravind Iddamsetty
2025-07-30 9:08 ` Michal Wajdeczko
@ 2025-07-30 19:59 ` Rodrigo Vivi
1 sibling, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2025-07-30 19:59 UTC (permalink / raw)
To: Aravind Iddamsetty
Cc: intel-xe, riana.tauro, himal.prasad.ghimiray, anshuman.gupta
On Wed, Jul 30, 2025 at 11:18:05AM +0530, Aravind Iddamsetty wrote:
> From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
> The GFX device reports two classes of errors: uncorrectable and
> correctable. Depending on the severity uncorrectable errors are
> further classified as non fatal and fatal. Driver will only handle
> logging of errors and updating counters from various components within
> the graphics device. Anything more will be handled at system level.
>
> Correctable and NonFatal errors are reported as interrupts, bits in
> the Master Interrupt Register will be used to convey the class of error.
> Determine source of error (IP block) by reading the Device Error Source
> Register (RW1C) that corresponds to the class of error being serviced
>
> Fatal errors are reported as PCIe errors. When a PCIe error is asserted,
> the OS will perform a device warm reset which causes the driver to
> reload. The error registers are sticky and the values are maintained
> through a warm reset. We read these registers during the boot flow of the
> driver and increment the respective error counters.
>
> Bspec: 50875, 53073, 53074, 53075, 53076
>
> v6
> - Limit the implementation to DG2 and PVC.
> - Limit the tile level logging to only PVC.
> - Use xarray instead of array for error counters.
> - Squash the fatal error reporting patch with this patch.
> - use drm_dbg instead of drm_info to dump register values.
> - use XE_HW_ERR_UNSPEC for error which are reported by leaf registers.
> - use source_typeoferror_errorname convention for enum and error loging.
> - Clean unused enums and there are no display supported ras error,
> categorize them as unknown.
> - Dont make xe_assign_hw_err_regs static.
> - Use err_name_index_pair instead of err_msg_cntr_pair.(Aravind)
>
> v7
> - Ci fix
>
> v8
> - Avoid unnecessary write if reg is empty incase of DG2.
>
> v9
> - For reg being blank print error for DG2 too.
> - Maintain order of headers.
> - Make XE_HW_ERR_UNSPEC 0. (Aravind)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
please remember to sign-off every patch from others that you are handling
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> drivers/gpu/drm/xe/regs/xe_regs.h | 3 +
> drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 13 +
> drivers/gpu/drm/xe/xe_device.c | 13 +
> drivers/gpu/drm/xe/xe_device_types.h | 10 +
> drivers/gpu/drm/xe/xe_hw_error.c | 258 +++++++++++++++++++
> drivers/gpu/drm/xe/xe_hw_error.h | 50 ++++
> drivers/gpu/drm/xe/xe_irq.c | 1 +
> drivers/gpu/drm/xe/xe_tile.c | 2 +
> 10 files changed, 352 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
> create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 42c6ca5b3f76..80eecd35e807 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -82,6 +82,7 @@ xe-y += xe_bb.o \
> xe_hw_engine.o \
> xe_hw_engine_class_sysfs.o \
> xe_hw_engine_group.o \
> + xe_hw_error.o \
> xe_hw_fence.o \
> xe_irq.o \
> xe_lrc.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 13635e4331d4..086ec7584b1a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -18,6 +18,7 @@
> #define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF)
> #define MASTER_IRQ REG_BIT(31)
> #define GU_MISC_IRQ REG_BIT(29)
> +#define XE_ERROR_IRQ(x) REG_BIT(26 + (x))
> #define DISPLAY_IRQ REG_BIT(16)
> #define I2C_IRQ REG_BIT(12)
> #define GT_DW_IRQ(x) REG_BIT(x)
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 1926b4044314..00900d3821f7 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -9,6 +9,9 @@
>
> #define SOC_BASE 0x280000
>
> +#define DEV_PCIEERR_STATUS XE_REG(0x100180)
> +#define DEV_PCIEERR_IS_FATAL(x) REG_BIT(x * 4 + 2)
> +
> #define GU_CNTL_PROTECTED XE_REG(0x10100C)
> #define DRIVERINT_FLR_DIS REG_BIT(31)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> new file mode 100644
> index 000000000000..ba5480fb2789
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef XE_TILE_ERROR_REGS_H_
> +#define XE_TILE_ERROR_REGS_H_
> +
> +#define _DEV_ERR_STAT_NONFATAL 0x100178
> +#define _DEV_ERR_STAT_CORRECTABLE 0x10017c
> +#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
> + _DEV_ERR_STAT_CORRECTABLE, \
> + _DEV_ERR_STAT_NONFATAL))
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index d04a0ae018e6..e0625fa5b1ca 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -875,6 +875,8 @@ int xe_device_probe(struct xe_device *xe)
> return err;
> }
>
> + xe_init_hw_errors(xe);
> +
> err = xe_irq_install(xe);
> if (err)
> return err;
> @@ -952,6 +954,15 @@ int xe_device_probe(struct xe_device *xe)
> return err;
> }
>
> +static void xe_hw_error_fini(struct xe_device *xe)
> +{
> + struct xe_tile *tile;
> + int i;
> +
> + for_each_tile(tile, xe, i)
> + xa_destroy(&tile->errors.hw_error);
> +}
> +
> void xe_device_remove(struct xe_device *xe)
> {
> xe_display_unregister(xe);
> @@ -961,6 +972,8 @@ void xe_device_remove(struct xe_device *xe)
> drm_dev_unplug(&xe->drm);
>
> xe_bo_pci_dev_remove_all(xe);
> +
> + xe_hw_error_fini(xe);
> }
>
> void xe_device_shutdown(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 38c8329b4d2c..233c2751d09f 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -14,6 +14,7 @@
>
> #include "xe_devcoredump_types.h"
> #include "xe_heci_gsc.h"
> +#include "xe_hw_error.h"
> #include "xe_lmtt_types.h"
> #include "xe_memirq_types.h"
> #include "xe_oa_types.h"
> @@ -206,6 +207,11 @@ struct xe_tile {
>
> /** @debugfs: debugfs directory associated with this tile */
> struct dentry *debugfs;
> +
> + /** @errors: count of hardware errors reported for the tile */
> + struct tile_hw_errors {
> + struct xarray hw_error;
> + } errors;
> };
>
> /**
> @@ -575,6 +581,10 @@ struct xe_device {
> */
> atomic64_t global_total_pages;
> #endif
> + /** @hw_err_regs: list of hw error regs*/
> + struct hardware_errors_regs {
> + const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
> + } hw_err_regs;
>
> /* private: */
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> new file mode 100644
> index 000000000000..84830ad81813
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -0,0 +1,258 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include "xe_hw_error.h"
> +
> +#include "regs/xe_regs.h"
> +#include "regs/xe_irq_regs.h"
> +#include "regs/xe_tile_error_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +
> +static const char *
> +hardware_error_type_to_str(const enum hardware_error hw_err)
> +{
> + switch (hw_err) {
> + case HARDWARE_ERROR_CORRECTABLE:
> + return "CORRECTABLE";
> + case HARDWARE_ERROR_NONFATAL:
> + return "NONFATAL";
> + case HARDWARE_ERROR_FATAL:
> + return "FATAL";
> + default:
> + return "UNKNOWN";
> + }
> +}
> +
> +static const struct err_name_index_pair dg2_err_stat_fatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [12] = {"SGUNIT", XE_HW_ERR_TILE_FATAL_SGUNIT},
> + [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 31] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair dg2_err_stat_nonfatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [12] = {"SGUNIT", XE_HW_ERR_TILE_NONFATAL_SGUNIT},
> + [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [20] = {"MERT", XE_HW_ERR_TILE_NONFATAL_MERT},
> + [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair dg2_err_stat_correctable_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 3] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [4 ... 7] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 11] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [12] = {"SGUNIT", XE_HW_ERR_TILE_CORR_SGUNIT},
> + [13 ... 15] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_fatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1] = {"SGGI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGGI},
> + [2 ... 7] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9] = {"SGLI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGLI},
> + [10 ... 12] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [13] = {"SGCI Cmd Parity", XE_HW_ERR_TILE_FATAL_SGCI},
> + [14 ... 15] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [16] = {"SOC ERROR", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> + [20] = {"MERT Cmd Parity", XE_HW_ERR_TILE_FATAL_MERT},
> + [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_FATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_nonfatal_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1] = {"SGGI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGGI},
> + [2 ... 7] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9] = {"SGLI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGLI},
> + [10 ... 12] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [13] = {"SGCI Data Parity", XE_HW_ERR_TILE_NONFATAL_SGCI},
> + [14 ... 15] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [16] = {"SOC", XE_HW_ERR_TILE_UNSPEC},
> + [17 ... 19] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> + [20] = {"MERT Data Parity", XE_HW_ERR_TILE_NONFATAL_MERT},
> + [21 ... 31] = {"Undefined", XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
> + [0] = {"GT", XE_HW_ERR_TILE_UNSPEC},
> + [1 ... 7] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> + [8] = {"GSC", XE_HW_ERR_TILE_UNSPEC},
> + [9 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
> +};
> +
> +static void xe_assign_hw_err_regs(struct xe_device *xe)
> +{
> + const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> +
> + /* Error reporting is supported only for DG2 and PVC currently. */
what about BMG? It is strange that DG2 has it but BMG hasn't...
> + if (xe->info.platform == XE_DG2) {
> + dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
> + dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
> + dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
> + }
> +
> + if (xe->info.platform == XE_PVC) {
> + dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
> + dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
> + dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
> + }
> +}
> +
> +static bool xe_platform_has_ras(struct xe_device *xe)
> +{
> + if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2)
> + return true;
> +
> + return false;
> +}
> +
> +static void
> +xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
> +{
> + unsigned long flags;
> + void *entry;
> +
> + entry = xa_load(hw_error, index);
> + entry = xa_mk_value(xa_to_value(entry) + 1);
> +
> + xa_lock_irqsave(hw_error, flags);
> + if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
> + drm_err_ratelimited(drm,
> + HW_ERR "Error reported by index %ld is lost\n", index);
> + xa_unlock_irqrestore(hw_error, flags);
> +}
> +
> +static void
> +xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
> +{
> + const char *hw_err_str = hardware_error_type_to_str(hw_err);
> + const struct hardware_errors_regs *err_regs;
> + const struct err_name_index_pair *errstat;
> + unsigned long errsrc;
> + unsigned long flags;
> + const char *name;
> + u32 indx;
> + u32 errbit;
> +
> + if (!xe_platform_has_ras(tile_to_xe(tile)))
> + return;
> +
> + spin_lock_irqsave(&tile_to_xe(tile)->irq.lock, flags);
> + err_regs = &tile_to_xe(tile)->hw_err_regs;
> + errstat = err_regs->dev_err_stat[hw_err];
> + errsrc = xe_mmio_read32(&tile->mmio, DEV_ERR_STAT_REG(hw_err));
> + if (!errsrc) {
> + drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
> + "TILE%d reported DEV_ERR_STAT_REG_%s blank!\n",
> + tile->id, hw_err_str);
> + goto unlock;
> + }
> +
> + if (tile_to_xe(tile)->info.platform != XE_DG2)
> + drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
> + "TILE%d reported DEV_ERR_STAT_REG_%s=0x%08lx\n",
> + tile->id, hw_err_str, errsrc);
> +
> + for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
> + name = errstat[errbit].name;
> + indx = errstat[errbit].index;
> +
> + if (hw_err == HARDWARE_ERROR_CORRECTABLE &&
> + tile_to_xe(tile)->info.platform != XE_DG2)
> + drm_warn(&tile_to_xe(tile)->drm,
> + HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
> + tile->id, name, hw_err_str, errbit);
> +
> + else if (tile_to_xe(tile)->info.platform != XE_DG2)
> + drm_err_ratelimited(&tile_to_xe(tile)->drm,
> + HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
> + tile->id, name, hw_err_str, errbit);
> +
> + if (indx != XE_HW_ERR_TILE_UNSPEC)
> + xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
> + &tile->errors.hw_error, indx);
> + }
> +
> + xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
> +unlock:
> + spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
> +}
> +
> +/*
> + * XE Platforms adds three Error bits to the Master Interrupt
> + * Register to support error handling. These three bits are
> + * used to convey the class of error:
> + * FATAL, NONFATAL, or CORRECTABLE.
> + *
> + * To process an interrupt:
> + * Determine source of error (IP block) by reading
> + * the Device Error Source Register (RW1C) that
> + * corresponds to the class of error being serviced
> + * and log the error.
> + */
> +void
> +xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
> +{
> + enum hardware_error hw_err;
> +
> + for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
> + if (master_ctl & XE_ERROR_IRQ(hw_err))
> + xe_hw_error_source_handler(tile, hw_err);
> + }
> +}
> +
> +/*
> + * xe_process_hw_errors - checks for the occurrence of HW errors
> + *
> + * Fatal will result in a card warm reset and driver will be reloaded.
> + * This checks for the HW Errors that might have occurred in the
> + * previous boot of the driver.
> + */
> +static void xe_process_hw_errors(struct xe_device *xe)
> +{
> + struct xe_mmio *root_mmio = xe_root_tile_mmio(xe);
> +
> + u32 dev_pcieerr_status, master_ctl;
> + struct xe_tile *tile;
> + int i;
> +
> + dev_pcieerr_status = xe_mmio_read32(root_mmio, DEV_PCIEERR_STATUS);
> +
> + for_each_tile(tile, xe, i) {
> + if (dev_pcieerr_status & DEV_PCIEERR_IS_FATAL(i))
> + xe_hw_error_source_handler(tile, HARDWARE_ERROR_FATAL);
> +
> + master_ctl = xe_mmio_read32(&tile->mmio, GFX_MSTR_IRQ);
> + xe_hw_error_irq_handler(tile, master_ctl);
> + xe_mmio_write32(&tile->mmio, GFX_MSTR_IRQ, master_ctl);
> + }
> + if (dev_pcieerr_status)
> + xe_mmio_write32(root_mmio, DEV_PCIEERR_STATUS, dev_pcieerr_status);
> +}
> +
> +void xe_init_hw_errors(struct xe_device *xe)
> +{
> + xe_assign_hw_err_regs(xe);
> + xe_process_hw_errors(xe);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> new file mode 100644
> index 000000000000..398e2a7f2ac6
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef XE_HW_ERRORS_H_
> +#define XE_HW_ERRORS_H_
> +
> +#include <linux/stddef.h>
> +#include <linux/types.h>
> +
> +#define XE_RAS_REG_SIZE 32
> +
> +/* Error categories reported by hardware */
> +enum hardware_error {
> + HARDWARE_ERROR_CORRECTABLE = 0,
> + HARDWARE_ERROR_NONFATAL = 1,
> + HARDWARE_ERROR_FATAL = 2,
> + HARDWARE_ERROR_MAX,
> +};
> +
> +/* Count of Correctable and Uncorrectable errors reported on tile */
> +enum xe_tile_hw_errors {
> + XE_HW_ERR_TILE_UNSPEC = 0,
> + XE_HW_ERR_TILE_FATAL_SGGI,
> + XE_HW_ERR_TILE_FATAL_SGLI,
> + XE_HW_ERR_TILE_FATAL_SGUNIT,
> + XE_HW_ERR_TILE_FATAL_SGCI,
> + XE_HW_ERR_TILE_FATAL_MERT,
> + XE_HW_ERR_TILE_FATAL_UNKNOWN,
> + XE_HW_ERR_TILE_NONFATAL_SGGI,
> + XE_HW_ERR_TILE_NONFATAL_SGLI,
> + XE_HW_ERR_TILE_NONFATAL_SGUNIT,
> + XE_HW_ERR_TILE_NONFATAL_SGCI,
> + XE_HW_ERR_TILE_NONFATAL_MERT,
> + XE_HW_ERR_TILE_NONFATAL_UNKNOWN,
> + XE_HW_ERR_TILE_CORR_SGUNIT,
> + XE_HW_ERR_TILE_CORR_UNKNOWN,
> +};
> +
> +struct err_name_index_pair {
> + const char *name;
> + const u32 index;
> +};
> +
> +struct xe_device;
> +struct xe_tile;
> +
> +void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
> +void xe_init_hw_errors(struct xe_device *xe);
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 5df5b8c2a3e4..1e9cfb8bb85d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -468,6 +468,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
>
> gt_irq_handler(tile, master_ctl, intr_dw, identity);
> + xe_hw_error_irq_handler(tile, master_ctl);
>
> /*
> * Display interrupts (including display backlight operations
> diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
> index d49ba3401963..b00c517e5559 100644
> --- a/drivers/gpu/drm/xe/xe_tile.c
> +++ b/drivers/gpu/drm/xe/xe_tile.c
> @@ -91,6 +91,8 @@
> */
> static int xe_tile_alloc(struct xe_tile *tile)
> {
> + xa_init(&tile->errors.hw_error);
> +
> tile->mem.ggtt = xe_ggtt_alloc(tile);
> if (!tile->mem.ggtt)
> return -ENOMEM;
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 02/10] drm/xe: Add new helpers to log hardware errrors.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 01/10] drm/xe: Handle errors from various components Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 8:55 ` Michal Wajdeczko
2025-07-30 5:48 ` [PATCH 03/10] drm/xe: Log and count the GT hardware errors Aravind Iddamsetty
` (11 subsequent siblings)
13 siblings, 1 reply; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Introducing xe_gt_log_hw_err and xe_gt_log_hw_err helper to
report gt specific hardware errors.
v2
- use _gt and _fmt instead of gt and fmt.
- Messages should be same.
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/xe_gt_printk.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
index 11da0228cea7..2f9baf7d191b 100644
--- a/drivers/gpu/drm/xe/xe_gt_printk.h
+++ b/drivers/gpu/drm/xe/xe_gt_printk.h
@@ -46,6 +46,13 @@
#define xe_gt_WARN_ON_ONCE(_gt, _condition) \
xe_gt_WARN_ONCE((_gt), _condition, "%s(%s)", "gt_WARN_ON_ONCE", __stringify(_condition))
+#define xe_gt_log_hw_err(_gt, _fmt, ...) \
+ drm_err_ratelimited(>_to_xe(_gt)->drm, HW_ERR "GT%d reported " _fmt, \
+ (_gt)->info.id, ##__VA_ARGS__)
+
+#define xe_gt_log_hw_warn(_gt, _fmt, ...) \
+ drm_warn(>_to_xe(_gt)->drm, HW_ERR "GT%d reported " _fmt, (_gt)->info.id, ##__VA_ARGS__)
+
static inline void __xe_gt_printfn_err(struct drm_printer *p, struct va_format *vaf)
{
struct xe_gt *gt = p->arg;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 02/10] drm/xe: Add new helpers to log hardware errrors.
2025-07-30 5:48 ` [PATCH 02/10] drm/xe: Add new helpers to log hardware errrors Aravind Iddamsetty
@ 2025-07-30 8:55 ` Michal Wajdeczko
0 siblings, 0 replies; 18+ messages in thread
From: Michal Wajdeczko @ 2025-07-30 8:55 UTC (permalink / raw)
To: Aravind Iddamsetty, intel-xe
Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
On 7/30/2025 7:48 AM, Aravind Iddamsetty wrote:
> From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
> Introducing xe_gt_log_hw_err and xe_gt_log_hw_err helper to
> report gt specific hardware errors.
>
> v2
> - use _gt and _fmt instead of gt and fmt.
> - Messages should be same.
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_printk.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
> index 11da0228cea7..2f9baf7d191b 100644
> --- a/drivers/gpu/drm/xe/xe_gt_printk.h
> +++ b/drivers/gpu/drm/xe/xe_gt_printk.h
> @@ -46,6 +46,13 @@
> #define xe_gt_WARN_ON_ONCE(_gt, _condition) \
> xe_gt_WARN_ONCE((_gt), _condition, "%s(%s)", "gt_WARN_ON_ONCE", __stringify(_condition))
>
> +#define xe_gt_log_hw_err(_gt, _fmt, ...) \
> + drm_err_ratelimited(>_to_xe(_gt)->drm, HW_ERR "GT%d reported " _fmt, \
> + (_gt)->info.id, ##__VA_ARGS__)
> +
> +#define xe_gt_log_hw_warn(_gt, _fmt, ...) \
> + drm_warn(>_to_xe(_gt)->drm, HW_ERR "GT%d reported " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> +
hmm, I'm not sure this is right place for such specific helpers
please consider moving them to xe_gt_hw_err.h or at least redef as:
#include "xe_gt_printk.h"
#define xe_gt_hw_err(_gt, _fmt, ...) \
xe_gt_err_ratelimited((_gt), HW_ERR _fmt, ##__VA_ARGS__)
#define xe_gt_hw_warn(_gt, _fmt, ...) \
xe_gt_warn((_gt), HW_ERR _fmt, ##__VA_ARGS__)
as likely the output as below is also acceptable:
[] xe 0000:8c:00.0: [drm] *ERROR* GT1: [Hardware Error]: blah blah
vs yours
[] xe 0000:8c:00.0: [drm] *ERROR* [Hardware Error]: GT1 reported blah blah
> static inline void __xe_gt_printfn_err(struct drm_printer *p, struct va_format *vaf)
> {
> struct xe_gt *gt = p->arg;
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 03/10] drm/xe: Log and count the GT hardware errors.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 01/10] drm/xe: Handle errors from various components Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 02/10] drm/xe: Add new helpers to log hardware errrors Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 04/10] drm/xe: Support GT hardware error reporting for PVC Aravind Iddamsetty
` (10 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
For the errors reported by GT unit, read the GT error register.
Log and count these errors and clear the error register.
Bspec: 53088, 53089, 53090
v6
- define the BIT and use it.
- Limit the GT error reporting to DG2 and PVC only.
- Rename function to xe_gt_hw_error_log_status_reg from
xe_gt_hw_error_status_reg_handler. (Aravind)
v7
- ci fixes
v8
- Initialize xarray only for primary gt.
- maintain header orders.
- Use new defined helper for gt error loging. (Aravind)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_error_regs.h | 13 +++
drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 1 +
drivers/gpu/drm/xe/xe_device.c | 5 +-
drivers/gpu/drm/xe/xe_device_types.h | 1 +
drivers/gpu/drm/xe/xe_gt.c | 1 +
drivers/gpu/drm/xe/xe_gt_types.h | 6 ++
drivers/gpu/drm/xe/xe_hw_error.c | 94 ++++++++++++++++++++
drivers/gpu/drm/xe/xe_hw_error.h | 23 +++++
8 files changed, 143 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
new file mode 100644
index 000000000000..6180704a6149
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_GT_ERROR_REGS_H_
+#define XE_GT_ERROR_REGS_H_
+
+#define _ERR_STAT_GT_COR 0x100160
+#define _ERR_STAT_GT_NONFATAL 0x100164
+#define ERR_STAT_GT_REG(x) XE_REG(_PICK_EVEN((x), \
+ _ERR_STAT_GT_COR, \
+ _ERR_STAT_GT_NONFATAL))
+#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index ba5480fb2789..45bd6b85e115 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -10,4 +10,5 @@
#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
_DEV_ERR_STAT_CORRECTABLE, \
_DEV_ERR_STAT_NONFATAL))
+#define XE_GT_ERROR 0
#endif
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index e0625fa5b1ca..806dbdf8118c 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -959,8 +959,11 @@ static void xe_hw_error_fini(struct xe_device *xe)
struct xe_tile *tile;
int i;
- for_each_tile(tile, xe, i)
+ for_each_tile(tile, xe, i) {
xa_destroy(&tile->errors.hw_error);
+ xa_destroy(&tile->primary_gt->errors.hw_error);
+ }
+
}
void xe_device_remove(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 233c2751d09f..4c7fb0d021c2 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -584,6 +584,7 @@ struct xe_device {
/** @hw_err_regs: list of hw error regs*/
struct hardware_errors_regs {
const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
} hw_err_regs;
/* private: */
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index c8eda36546d3..919bdb378798 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -88,6 +88,7 @@ struct xe_gt *xe_gt_alloc(struct xe_tile *tile)
if (err)
return ERR_PTR(err);
+ xa_init(>->errors.hw_error);
return gt;
}
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index dfd4a16da5f0..a84baf22be70 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -13,6 +13,7 @@
#include "xe_gt_sriov_vf_types.h"
#include "xe_gt_stats_types.h"
#include "xe_hw_engine_types.h"
+#include "xe_hw_error.h"
#include "xe_hw_fence_types.h"
#include "xe_oa_types.h"
#include "xe_reg_sr_types.h"
@@ -449,6 +450,11 @@ struct xe_gt {
/** @eu_stall: EU stall counters subsystem per gt info */
struct xe_eu_stall_gt *eu_stall;
+
+ /** @errors: count of hardware errors reported for the gt */
+ struct gt_hw_errors {
+ struct xarray hw_error;
+ } errors;
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 84830ad81813..66a1a0c288f8 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -3,8 +3,10 @@
* Copyright © 2023 Intel Corporation
*/
+#include "xe_gt_printk.h"
#include "xe_hw_error.h"
+#include "regs/xe_gt_error_regs.h"
#include "regs/xe_regs.h"
#include "regs/xe_irq_regs.h"
#include "regs/xe_tile_error_regs.h"
@@ -101,15 +103,48 @@ static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
[9 ... 31] = {"Undefined", XE_HW_ERR_TILE_CORR_UNKNOWN},
};
+static const struct err_name_index_pair dg2_stat_gt_fatal_reg[] = {
+ [0] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [1] = {"Array BIST", XE_HW_ERR_GT_FATAL_ARR_BIST},
+ [2] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [3] = {"FPU", XE_HW_ERR_GT_FATAL_FPU},
+ [4] = {"L3 Double", XE_HW_ERR_GT_FATAL_L3_DOUB},
+ [5] = {"L3 ECC Checker", XE_HW_ERR_GT_FATAL_L3_ECC_CHK},
+ [6] = {"GUC SRAM", XE_HW_ERR_GT_FATAL_GUC},
+ [7] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [8] = {"IDI PARITY", XE_HW_ERR_GT_FATAL_IDI_PAR},
+ [9] = {"SQIDI", XE_HW_ERR_GT_FATAL_SQIDI},
+ [10 ... 11] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [12] = {"SAMPLER", XE_HW_ERR_GT_FATAL_SAMPLER},
+ [13] = {"SLM", XE_HW_ERR_GT_FATAL_SLM},
+ [14] = {"EU IC", XE_HW_ERR_GT_FATAL_EU_IC},
+ [15] = {"EU GRF", XE_HW_ERR_GT_FATAL_EU_GRF},
+ [16 ... 31] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair dg2_stat_gt_correctable_reg[] = {
+ [0] = {"L3 SINGLE", XE_HW_ERR_GT_CORR_L3_SNG},
+ [1] = {"SINGLE BIT GUC SRAM", XE_HW_ERR_GT_CORR_GUC},
+ [2 ... 11] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
+ [12] = {"SINGLE BIT SAMPLER", XE_HW_ERR_GT_CORR_SAMPLER},
+ [13] = {"SINGLE BIT SLM", XE_HW_ERR_GT_CORR_SLM},
+ [14] = {"SINGLE BIT EU IC", XE_HW_ERR_GT_CORR_EU_IC},
+ [15] = {"SINGLE BIT EU GRF", XE_HW_ERR_GT_CORR_EU_GRF},
+ [16 ... 31] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
+};
+
static void xe_assign_hw_err_regs(struct xe_device *xe)
{
const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
+ const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
/* Error reporting is supported only for DG2 and PVC currently. */
if (xe->info.platform == XE_DG2) {
dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
+ err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = dg2_stat_gt_correctable_reg;
+ err_stat_gt[HARDWARE_ERROR_FATAL] = dg2_stat_gt_fatal_reg;
}
if (xe->info.platform == XE_PVC) {
@@ -117,6 +152,7 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
}
+
}
static bool xe_platform_has_ras(struct xe_device *xe)
@@ -143,6 +179,62 @@ xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned
xa_unlock_irqrestore(hw_error, flags);
}
+static void
+xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+ const char *hw_err_str = hardware_error_type_to_str(hw_err);
+ const struct err_name_index_pair *errstat;
+ struct hardware_errors_regs *err_regs;
+ unsigned long errsrc;
+ const char *name;
+ u32 indx;
+ u32 errbit;
+
+ err_regs = >_to_xe(gt)->hw_err_regs;
+ errsrc = xe_mmio_read32(>->tile->mmio, ERR_STAT_GT_REG(hw_err));
+ if (!errsrc) {
+ xe_gt_log_hw_err(gt, "ERR_STAT_GT_REG_%s blank!\n", hw_err_str);
+ return;
+ }
+
+ drm_dbg(>_to_xe(gt)->drm, HW_ERR "GT%d ERR_STAT_GT_REG_%s=0x%08lx\n",
+ gt->info.id, hw_err_str, errsrc);
+
+ if (hw_err == HARDWARE_ERROR_NONFATAL) {
+ /* The GT Non Fatal Error Status Register has only reserved bits
+ * Nothing to service.
+ */
+ xe_gt_log_hw_err(gt, "%s error\n", hw_err_str);
+ goto clear_reg;
+ }
+
+ errstat = err_regs->err_stat_gt[hw_err];
+ for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
+ name = errstat[errbit].name;
+ indx = errstat[errbit].index;
+
+ if (hw_err == HARDWARE_ERROR_FATAL)
+ xe_gt_log_hw_err(gt, "%s %s error, bit[%d] is set\n",
+ name, hw_err_str, errbit);
+ else
+ xe_gt_log_hw_err(gt, "%s %s error, bit[%d] is set\n",
+ name, hw_err_str, errbit);
+
+ xe_update_hw_error_cnt(>_to_xe(gt)->drm, >->errors.hw_error, indx);
+ }
+clear_reg:
+ xe_mmio_write32(>->tile->mmio, ERR_STAT_GT_REG(hw_err), errsrc);
+}
+
+static void
+xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+ lockdep_assert_held(>_to_xe(gt)->irq.lock);
+
+ if (gt_to_xe(gt)->info.platform == XE_DG2)
+ xe_gt_hw_error_log_status_reg(gt, hw_err);
+}
+
static void
xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
{
@@ -192,6 +284,8 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
if (indx != XE_HW_ERR_TILE_UNSPEC)
xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
&tile->errors.hw_error, indx);
+ if (errbit == XE_GT_ERROR)
+ xe_gt_hw_error_handler(tile->primary_gt, hw_err);
}
xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 398e2a7f2ac6..3dc32dbfc8bb 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -37,6 +37,29 @@ enum xe_tile_hw_errors {
XE_HW_ERR_TILE_CORR_UNKNOWN,
};
+/* Count of GT Correctable and FATAL HW ERRORS */
+enum xe_gt_hw_errors {
+ XE_HW_ERR_GT_CORR_L3_SNG,
+ XE_HW_ERR_GT_CORR_GUC,
+ XE_HW_ERR_GT_CORR_SAMPLER,
+ XE_HW_ERR_GT_CORR_SLM,
+ XE_HW_ERR_GT_CORR_EU_IC,
+ XE_HW_ERR_GT_CORR_EU_GRF,
+ XE_HW_ERR_GT_CORR_UNKNOWN,
+ XE_HW_ERR_GT_FATAL_ARR_BIST,
+ XE_HW_ERR_GT_FATAL_FPU,
+ XE_HW_ERR_GT_FATAL_L3_DOUB,
+ XE_HW_ERR_GT_FATAL_L3_ECC_CHK,
+ XE_HW_ERR_GT_FATAL_GUC,
+ XE_HW_ERR_GT_FATAL_IDI_PAR,
+ XE_HW_ERR_GT_FATAL_SQIDI,
+ XE_HW_ERR_GT_FATAL_SAMPLER,
+ XE_HW_ERR_GT_FATAL_SLM,
+ XE_HW_ERR_GT_FATAL_EU_IC,
+ XE_HW_ERR_GT_FATAL_EU_GRF,
+ XE_HW_ERR_GT_FATAL_UNKNOWN,
+};
+
struct err_name_index_pair {
const char *name;
const u32 index;
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 04/10] drm/xe: Support GT hardware error reporting for PVC.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (2 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 03/10] drm/xe: Log and count the GT hardware errors Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 05/10] drm/xe: Support GSC " Aravind Iddamsetty
` (9 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
PVC supports GT error reporting via vector registers alongwith
error status register. Add support to report these errors and
update respective counters.
Incase of Subslice error reported by vector register, process the
error status register for applicable bits.
Bspec: 54179, 54177, 53088, 53089
v6
- Define registers ascending order of their addresses.
- use xe_gt_hw_error_log_vector_reg instead of
xe_gt_hw_error_vectr_reg_handler.
- use xe_assign_hw_err_regs for reg initialization.
- use switch-case instead of if-else.
v7
- Use all vctr for correctable too.
- Use helper functions to log gt hardware errors. (Aravind)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_error_regs.h | 16 +++
drivers/gpu/drm/xe/xe_device_types.h | 1 +
drivers/gpu/drm/xe/xe_hw_error.c | 124 ++++++++++++++++++++-
drivers/gpu/drm/xe/xe_hw_error.h | 19 ++++
4 files changed, 158 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
index 6180704a6149..59631c2e8e12 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
@@ -10,4 +10,20 @@
#define ERR_STAT_GT_REG(x) XE_REG(_PICK_EVEN((x), \
_ERR_STAT_GT_COR, \
_ERR_STAT_GT_NONFATAL))
+
+#define _ERR_STAT_GT_FATAL_VCTR_0 0x100260
+#define _ERR_STAT_GT_FATAL_VCTR_1 0x100264
+#define ERR_STAT_GT_FATAL_VCTR_REG(x) XE_REG(_PICK_EVEN((x), \
+ _ERR_STAT_GT_FATAL_VCTR_0, \
+ _ERR_STAT_GT_FATAL_VCTR_1))
+
+#define _ERR_STAT_GT_COR_VCTR_0 0x1002a0
+#define _ERR_STAT_GT_COR_VCTR_1 0x1002a4
+#define ERR_STAT_GT_COR_VCTR_REG(x) XE_REG(_PICK_EVEN((x), \
+ _ERR_STAT_GT_COR_VCTR_0, \
+ _ERR_STAT_GT_COR_VCTR_1))
+
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+ ERR_STAT_GT_COR_VCTR_REG(x) : \
+ ERR_STAT_GT_FATAL_VCTR_REG(x))
#endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4c7fb0d021c2..7b93335b58f1 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -585,6 +585,7 @@ struct xe_device {
struct hardware_errors_regs {
const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
} hw_err_regs;
/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 66a1a0c288f8..5325557b2931 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -133,10 +133,47 @@ static const struct err_name_index_pair dg2_stat_gt_correctable_reg[] = {
[16 ... 31] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
};
+static const struct err_name_index_pair pvc_err_stat_gt_fatal_reg[] = {
+ [0 ... 2] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [3] = {"FPU", XE_HW_ERR_GT_FATAL_FPU},
+ [4 ... 5] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [6] = {"GUC SRAM", XE_HW_ERR_GT_FATAL_GUC},
+ [7 ... 12] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [13] = {"SLM", XE_HW_ERR_GT_FATAL_SLM},
+ [14] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [15] = {"EU GRF", XE_HW_ERR_GT_FATAL_EU_GRF},
+ [16 ... 31] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_gt_correctable_reg[] = {
+ [0] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
+ [1] = {"SINGLE BIT GUC SRAM", XE_HW_ERR_GT_CORR_GUC},
+ [2 ... 12] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
+ [13] = {"SINGLE BIT SLM", XE_HW_ERR_GT_CORR_SLM},
+ [14] = {"SINGLE BIT EU IC", XE_HW_ERR_GT_CORR_EU_IC},
+ [15] = {"SINGLE BIT EU GRF", XE_HW_ERR_GT_CORR_EU_GRF},
+ [16 ... 31] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_vectr_gt_fatal_reg[] = {
+ [0 ... 1] = {"SUBSLICE", XE_HW_ERR_GT_FATAL_SUBSLICE},
+ [2 ... 3] = {"L3BANK", XE_HW_ERR_GT_FATAL_L3BANK},
+ [4 ... 5] = {"Undefined", XE_HW_ERR_GT_FATAL_UNKNOWN},
+ [6] = {"TLB", XE_HW_ERR_GT_FATAL_TLB},
+ [7] = {"L3 FABRIC", XE_HW_ERR_GT_FATAL_L3_FABRIC},
+};
+
+static const struct err_name_index_pair pvc_err_vectr_gt_correctable_reg[] = {
+ [0 ... 1] = {"SUBSLICE", XE_HW_ERR_GT_CORR_SUBSLICE},
+ [2 ... 3] = {"L3BANK", XE_HW_ERR_GT_CORR_L3BANK},
+ [4 ... 7] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
+};
+
static void xe_assign_hw_err_regs(struct xe_device *xe)
{
const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
+ const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
/* Error reporting is supported only for DG2 and PVC currently. */
if (xe->info.platform == XE_DG2) {
@@ -151,6 +188,10 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
+ err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_gt_correctable_reg;
+ err_stat_gt[HARDWARE_ERROR_FATAL] = pvc_err_stat_gt_fatal_reg;
+ err_vctr_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_vectr_gt_correctable_reg;
+ err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
}
}
@@ -164,13 +205,14 @@ static bool xe_platform_has_ras(struct xe_device *xe)
}
static void
-xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
+xe_update_hw_error_cnt_with_value(struct drm_device *drm, struct xarray *hw_error,
+ unsigned long index, unsigned long val)
{
unsigned long flags;
void *entry;
entry = xa_load(hw_error, index);
- entry = xa_mk_value(xa_to_value(entry) + 1);
+ entry = xa_mk_value(xa_to_value(entry) + val);
xa_lock_irqsave(hw_error, flags);
if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
@@ -179,6 +221,12 @@ xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned
xa_unlock_irqrestore(hw_error, flags);
}
+static void
+xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
+{
+ xe_update_hw_error_cnt_with_value(drm, hw_error, index, 1);
+}
+
static void
xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err)
{
@@ -190,6 +238,7 @@ xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err
u32 indx;
u32 errbit;
+ lockdep_assert_held(>_to_xe(gt)->irq.lock);
err_regs = >_to_xe(gt)->hw_err_regs;
errsrc = xe_mmio_read32(>->tile->mmio, ERR_STAT_GT_REG(hw_err));
if (!errsrc) {
@@ -226,6 +275,74 @@ xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err
xe_mmio_write32(>->tile->mmio, ERR_STAT_GT_REG(hw_err), errsrc);
}
+static void
+xe_gt_hw_error_log_vector_reg(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+ const char *hw_err_str = hardware_error_type_to_str(hw_err);
+ const struct err_name_index_pair *errvctr;
+ struct hardware_errors_regs *err_regs;
+ const char *name;
+ bool errstat_read;
+ unsigned long val;
+ u32 num_vctr_reg;
+ u32 indx;
+ u32 vctr;
+ u32 i;
+
+ if (hw_err == HARDWARE_ERROR_NONFATAL) {
+ /* The GT Non Fatal Error Status Register has only reserved bits
+ * Nothing to service.
+ */
+ xe_gt_log_hw_err(gt, "%s error\n", hw_err_str);
+ return;
+ }
+
+ errstat_read = false;
+ num_vctr_reg = ERR_STAT_GT_VCTR_LEN;
+ err_regs = >_to_xe(gt)->hw_err_regs;
+ errvctr = err_regs->err_vctr_gt[hw_err];
+ for (i = 0 ; i < num_vctr_reg; i++) {
+ vctr = xe_mmio_read32(>->tile->mmio, ERR_STAT_GT_VCTR_REG(hw_err, i));
+ if (!vctr)
+ continue;
+
+ name = errvctr[i].name;
+ indx = errvctr[i].index;
+
+ if (hw_err == HARDWARE_ERROR_FATAL)
+ xe_gt_log_hw_err(gt, "%s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
+ name, hw_err_str, hw_err_str, i, vctr);
+ else
+ xe_gt_log_hw_warn(gt, "%s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
+ name, hw_err_str, hw_err_str, i, vctr);
+
+ switch (i) {
+ case ERR_STAT_GT_VCTR0:
+ case ERR_STAT_GT_VCTR1:
+ case ERR_STAT_GT_VCTR2:
+ case ERR_STAT_GT_VCTR3:
+ val = hweight32(vctr);
+ if (i < ERR_STAT_GT_VCTR2 && !errstat_read) {
+ xe_gt_hw_error_log_status_reg(gt, hw_err);
+ errstat_read = true;
+ }
+ xe_update_hw_error_cnt_with_value(>_to_xe(gt)->drm,
+ >->errors.hw_error, indx, val);
+ break;
+ case ERR_STAT_GT_VCTR6:
+ case ERR_STAT_GT_VCTR7:
+ val = (i == ERR_STAT_GT_VCTR6) ? hweight16(vctr) : hweight8(vctr);
+ xe_update_hw_error_cnt_with_value(>_to_xe(gt)->drm,
+ >->errors.hw_error, indx, val);
+ break;
+ default:
+ break;
+ }
+
+ xe_mmio_write32(>->tile->mmio, ERR_STAT_GT_VCTR_REG(hw_err, i), vctr);
+ }
+}
+
static void
xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
{
@@ -233,6 +350,9 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
if (gt_to_xe(gt)->info.platform == XE_DG2)
xe_gt_hw_error_log_status_reg(gt, hw_err);
+
+ if (gt_to_xe(gt)->info.platform == XE_PVC)
+ xe_gt_hw_error_log_vector_reg(gt, hw_err);
}
static void
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 3dc32dbfc8bb..ff1c4671b589 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -10,6 +10,8 @@
#define XE_RAS_REG_SIZE 32
+#define ERR_STAT_GT_VCTR_LEN (8)
+
/* Error categories reported by hardware */
enum hardware_error {
HARDWARE_ERROR_CORRECTABLE = 0,
@@ -37,8 +39,21 @@ enum xe_tile_hw_errors {
XE_HW_ERR_TILE_CORR_UNKNOWN,
};
+enum gt_vctr_registers {
+ ERR_STAT_GT_VCTR0 = 0,
+ ERR_STAT_GT_VCTR1,
+ ERR_STAT_GT_VCTR2,
+ ERR_STAT_GT_VCTR3,
+ ERR_STAT_GT_VCTR4,
+ ERR_STAT_GT_VCTR5,
+ ERR_STAT_GT_VCTR6,
+ ERR_STAT_GT_VCTR7,
+};
+
/* Count of GT Correctable and FATAL HW ERRORS */
enum xe_gt_hw_errors {
+ XE_HW_ERR_GT_CORR_SUBSLICE,
+ XE_HW_ERR_GT_CORR_L3BANK,
XE_HW_ERR_GT_CORR_L3_SNG,
XE_HW_ERR_GT_CORR_GUC,
XE_HW_ERR_GT_CORR_SAMPLER,
@@ -46,6 +61,10 @@ enum xe_gt_hw_errors {
XE_HW_ERR_GT_CORR_EU_IC,
XE_HW_ERR_GT_CORR_EU_GRF,
XE_HW_ERR_GT_CORR_UNKNOWN,
+ XE_HW_ERR_GT_FATAL_SUBSLICE,
+ XE_HW_ERR_GT_FATAL_L3BANK,
+ XE_HW_ERR_GT_FATAL_TLB,
+ XE_HW_ERR_GT_FATAL_L3_FABRIC,
XE_HW_ERR_GT_FATAL_ARR_BIST,
XE_HW_ERR_GT_FATAL_FPU,
XE_HW_ERR_GT_FATAL_L3_DOUB,
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 05/10] drm/xe: Support GSC hardware error reporting for PVC.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (3 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 04/10] drm/xe: Support GT hardware error reporting for PVC Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 06/10] drm/xe: Support SOC FATAL error handling " Aravind Iddamsetty
` (8 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Add support to report GSC hw errors and counter update in case
of correctable errors.
v2
- skip FW_ERR reporting via counters.
- maintain uniform naming for enums.
- Use same convention for error reporting.(Aravind)
v3
- Move gsc error in same enum as tile.
- Leave blankline before comments.
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 11 +++
drivers/gpu/drm/xe/xe_device_types.h | 1 +
drivers/gpu/drm/xe/xe_hw_error.c | 96 ++++++++++++++++++++
drivers/gpu/drm/xe/xe_hw_error.h | 14 +++
4 files changed, 122 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 45bd6b85e115..3ab28b321622 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -5,10 +5,21 @@
#ifndef XE_TILE_ERROR_REGS_H_
#define XE_TILE_ERROR_REGS_H_
+
+#define _GSC_HEC_UNCOR_ERR_STATUS 0x118
+#define _GSC_HEC_CORR_ERR_STATUS 0x128
+#define GSC_HEC_ERR_STAT_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _GSC_HEC_CORR_ERR_STATUS, \
+ (base) + _GSC_HEC_UNCOR_ERR_STATUS))
+
#define _DEV_ERR_STAT_NONFATAL 0x100178
#define _DEV_ERR_STAT_CORRECTABLE 0x10017c
#define DEV_ERR_STAT_REG(x) XE_REG(_PICK_EVEN((x), \
_DEV_ERR_STAT_CORRECTABLE, \
_DEV_ERR_STAT_NONFATAL))
#define XE_GT_ERROR 0
+#define XE_GSC_ERROR 8
+
+#define PVC_GSC_HECI1_BASE 0x284000
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 7b93335b58f1..5d5a730688d3 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -586,6 +586,7 @@ struct xe_device {
const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *gsc_error[HARDWARE_ERROR_MAX];
} hw_err_regs;
/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 5325557b2931..2aff84339534 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -169,11 +169,34 @@ static const struct err_name_index_pair pvc_err_vectr_gt_correctable_reg[] = {
[4 ... 7] = {"Undefined", XE_HW_ERR_GT_CORR_UNKNOWN},
};
+static const struct err_name_index_pair pvc_gsc_nonfatal_err_reg[] = {
+ [0] = {"MinuteIA Unexpected Shutdown", XE_HW_ERR_GSC_NONFATAL_MIA_SHUTDOWN},
+ [1] = {"MinuteIA Internal Error", XE_HW_ERR_GSC_NONFATAL_MIA_INTERNAL},
+ [2] = {"Double bit error on SRAM", XE_HW_ERR_GSC_NONFATAL_SRAM},
+ [3] = {"WDT 2nd Timeout", XE_HW_ERR_GSC_NONFATAL_WDG},
+ [4] = {"ROM has a parity error", XE_HW_ERR_GSC_NONFATAL_ROM_PARITY},
+ [5] = {"Ucode has a parity error", XE_HW_ERR_GSC_NONFATAL_UCODE_PARITY},
+ [6] = {"Errors Reported to and Detected by FW", XE_HW_ERR_TILE_UNSPEC},
+ [7] = {"Glitch is detected on voltage rail", XE_HW_ERR_GSC_NONFATAL_VLT_GLITCH},
+ [8] = {"Fuse Pull Error", XE_HW_ERR_GSC_NONFATAL_FUSE_PULL},
+ [9] = {"Fuse CRC Check Failed on Fuse Pull", XE_HW_ERR_GSC_NONFATAL_FUSE_CRC},
+ [10] = {"Self Mbist Failed", XE_HW_ERR_GSC_NONFATAL_SELF_MBIST},
+ [11] = {"AON RF has parity error", XE_HW_ERR_GSC_NONFATAL_AON_RF_PARITY},
+ [12 ... 31] = {"Undefined", XE_HW_ERR_GSC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_gsc_correctable_err_reg[] = {
+ [0] = {"Single bit error on SRAM", XE_HW_ERR_GSC_CORR_SRAM},
+ [1] = {"Errors Reported to FW and Detected by FW", XE_HW_ERR_TILE_UNSPEC},
+ [2 ... 31] = {"Undefined", XE_HW_ERR_GSC_CORR_UNKNOWN},
+};
+
static void xe_assign_hw_err_regs(struct xe_device *xe)
{
const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
+ const struct err_name_index_pair **gsc_error = xe->hw_err_regs.gsc_error;
/* Error reporting is supported only for DG2 and PVC currently. */
if (xe->info.platform == XE_DG2) {
@@ -192,6 +215,8 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
err_stat_gt[HARDWARE_ERROR_FATAL] = pvc_err_stat_gt_fatal_reg;
err_vctr_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_vectr_gt_correctable_reg;
err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
+ gsc_error[HARDWARE_ERROR_CORRECTABLE] = pvc_gsc_correctable_err_reg;
+ gsc_error[HARDWARE_ERROR_NONFATAL] = pvc_gsc_nonfatal_err_reg;
}
}
@@ -355,6 +380,73 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
xe_gt_hw_error_log_vector_reg(gt, hw_err);
}
+static void
+xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+ const char *hw_err_str = hardware_error_type_to_str(hw_err);
+ const struct err_name_index_pair *errstat;
+ struct hardware_errors_regs *err_regs;
+ struct xe_gt *gt;
+ unsigned long errsrc;
+ const char *name;
+ u32 indx;
+ u32 errbit;
+ u32 base;
+
+ if ((tile_to_xe(tile)->info.platform != XE_PVC))
+ return;
+
+ /*
+ * GSC errors are valid only on root tile and for NONFATAL and
+ * CORRECTABLE type.For non root tiles or FATAL type it should
+ * be categorized as undefined GSC HARDWARE ERROR
+ */
+ base = PVC_GSC_HECI1_BASE;
+
+ if (tile->id || hw_err == HARDWARE_ERROR_FATAL) {
+ drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported GSC %s Undefined error.\n",
+ tile->id, hw_err_str);
+ return;
+ }
+
+ lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
+ err_regs = &tile_to_xe(tile)->hw_err_regs;
+ errstat = err_regs->gsc_error[hw_err];
+ gt = tile->primary_gt;
+ errsrc = xe_mmio_read32(>->tile->mmio, GSC_HEC_ERR_STAT_REG(base, hw_err));
+ if (!errsrc) {
+ drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile0 reported GSC_HEC_ERR_STAT_REG_%s blank!\n", hw_err_str);
+ goto clear_reg;
+ }
+
+ drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile0 reported GSC_HEC_ERR_STAT_REG_%s=0x%08lx\n", hw_err_str, errsrc);
+
+ for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
+ name = errstat[errbit].name;
+ indx = errstat[errbit].index;
+
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+ drm_warn(&tile_to_xe(tile)->drm,
+ HW_ERR "Tile0 reported GSC %s %s error, bit[%d] is set\n",
+ name, hw_err_str, errbit);
+
+ } else {
+ drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile0 reported GSC %s %s error, bit[%d] is set\n",
+ name, hw_err_str, errbit);
+ }
+ if (indx != XE_HW_ERR_TILE_UNSPEC)
+ xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
+ &tile->errors.hw_error, indx);
+ }
+
+clear_reg:
+ xe_mmio_write32(>->tile->mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
+}
+
static void
xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
{
@@ -404,8 +496,12 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
if (indx != XE_HW_ERR_TILE_UNSPEC)
xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
&tile->errors.hw_error, indx);
+
if (errbit == XE_GT_ERROR)
xe_gt_hw_error_handler(tile->primary_gt, hw_err);
+
+ if (errbit == XE_GSC_ERROR)
+ xe_gsc_hw_error_handler(tile, hw_err);
}
xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index ff1c4671b589..20036a523963 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -37,6 +37,20 @@ enum xe_tile_hw_errors {
XE_HW_ERR_TILE_NONFATAL_UNKNOWN,
XE_HW_ERR_TILE_CORR_SGUNIT,
XE_HW_ERR_TILE_CORR_UNKNOWN,
+ XE_HW_ERR_GSC_CORR_SRAM,
+ XE_HW_ERR_GSC_CORR_UNKNOWN,
+ XE_HW_ERR_GSC_NONFATAL_MIA_SHUTDOWN,
+ XE_HW_ERR_GSC_NONFATAL_MIA_INTERNAL,
+ XE_HW_ERR_GSC_NONFATAL_SRAM,
+ XE_HW_ERR_GSC_NONFATAL_WDG,
+ XE_HW_ERR_GSC_NONFATAL_ROM_PARITY,
+ XE_HW_ERR_GSC_NONFATAL_UCODE_PARITY,
+ XE_HW_ERR_GSC_NONFATAL_VLT_GLITCH,
+ XE_HW_ERR_GSC_NONFATAL_FUSE_PULL,
+ XE_HW_ERR_GSC_NONFATAL_FUSE_CRC,
+ XE_HW_ERR_GSC_NONFATAL_SELF_MBIST,
+ XE_HW_ERR_GSC_NONFATAL_AON_RF_PARITY,
+ XE_HW_ERR_GSC_NONFATAL_UNKNOWN,
};
enum gt_vctr_registers {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/xe: Support SOC FATAL error handling for PVC.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (4 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 05/10] drm/xe: Support GSC " Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 07/10] drm/xe: Support SOC NONFATAL " Aravind Iddamsetty
` (7 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Report the SOC fatal hardware error and update the counters which will
increment incase of error.
v2
- Use xe_assign_hw_err_regs to initilaize registers.
- Use separate enums for SOC errors.
- Use xarray.
- No need to prepend register offsets with 0's.
- Dont use the counters if error is being reported by second level
registers.
- Fix Num of IEH to 2.
- define the bits along with respective register and use.
- Follow the convention source_typeoferror_errorname for enum and error
reporting.(Aravind)
v3
- Fix the condition check.
v4
- Make soc errors as part of tile_hw_errors.
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 32 ++++
drivers/gpu/drm/xe/xe_device_types.h | 4 +
drivers/gpu/drm/xe/xe_hw_error.c | 188 +++++++++++++++++++
drivers/gpu/drm/xe/xe_hw_error.h | 49 +++++
4 files changed, 273 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 3ab28b321622..31604138d511 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -11,6 +11,34 @@
#define GSC_HEC_ERR_STAT_REG(base, x) XE_REG(_PICK_EVEN((x), \
(base) + _GSC_HEC_CORR_ERR_STATUS, \
(base) + _GSC_HEC_UNCOR_ERR_STATUS))
+#define _SOC_GCOERRSTS 0x200
+#define _SOC_GNFERRSTS 0x210
+#define _SOC_GFAERRSTS 0x220
+#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _SOC_GCOERRSTS, \
+ (base) + _SOC_GNFERRSTS))
+#define SOC_IEH1_LOCAL_ERR_STATUS 0
+
+#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _SOC_GCOERRSTS, \
+ (base) + _SOC_GNFERRSTS))
+#define SOC_IEH0_LOCAL_ERR_STATUS 0
+#define SOC_IEH1_GLOBAL_ERR_STATUS 1
+
+#define _SOC_GSYSEVTCTL 0x264
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _SOC_GSYSEVTCTL, \
+ slave_base + _SOC_GSYSEVTCTL))
+
+#define _SOC_LERRCORSTS 0x294
+#define _SOC_LERRUNCSTS 0x280
+#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x) XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + _SOC_LERRUNCSTS : \
+ (base) + _SOC_LERRCORSTS)
+#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x) XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + _SOC_LERRUNCSTS : \
+ (base) + _SOC_LERRCORSTS)
+
#define _DEV_ERR_STAT_NONFATAL 0x100178
#define _DEV_ERR_STAT_CORRECTABLE 0x10017c
@@ -19,6 +47,10 @@
_DEV_ERR_STAT_NONFATAL))
#define XE_GT_ERROR 0
#define XE_GSC_ERROR 8
+#define XE_SOC_ERROR 16
+
+#define SOC_PVC_BASE 0x282000
+#define SOC_PVC_SLAVE_BASE 0x283000
#define PVC_GSC_HECI1_BASE 0x284000
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 5d5a730688d3..3a851c7a55dd 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -587,6 +587,10 @@ struct xe_device {
const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
const struct err_name_index_pair *gsc_error[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *soc_mstr_glbl[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *soc_mstr_lcl[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *soc_slave_glbl[HARDWARE_ERROR_MAX];
+ const struct err_name_index_pair *soc_slave_lcl[HARDWARE_ERROR_MAX];
} hw_err_regs;
/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 2aff84339534..927bf2ab401f 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -191,12 +191,85 @@ static const struct err_name_index_pair pvc_gsc_correctable_err_reg[] = {
[2 ... 31] = {"Undefined", XE_HW_ERR_GSC_CORR_UNKNOWN},
};
+static const struct err_name_index_pair pvc_soc_mstr_glbl_err_reg_fatal[] = {
+ [0] = {"MASTER LOCAL Reported", XE_HW_ERR_TILE_UNSPEC},
+ [1] = {"SLAVE GLOBAL Reported", XE_HW_ERR_TILE_UNSPEC},
+ [2] = {"HBM SS0: Channel0", XE_HW_ERR_SOC_FATAL_HBM0_CHNL0},
+ [3] = {"HBM SS0: Channel1", XE_HW_ERR_SOC_FATAL_HBM0_CHNL1},
+ [4] = {"HBM SS0: Channel2", XE_HW_ERR_SOC_FATAL_HBM0_CHNL2},
+ [5] = {"HBM SS0: Channel3", XE_HW_ERR_SOC_FATAL_HBM0_CHNL3},
+ [6] = {"HBM SS0: Channel4", XE_HW_ERR_SOC_FATAL_HBM0_CHNL4},
+ [7] = {"HBM SS0: Channel5", XE_HW_ERR_SOC_FATAL_HBM0_CHNL5},
+ [8] = {"HBM SS0: Channel6", XE_HW_ERR_SOC_FATAL_HBM0_CHNL6},
+ [9] = {"HBM SS0: Channel7", XE_HW_ERR_SOC_FATAL_HBM0_CHNL7},
+ [10] = {"HBM SS1: Channel0", XE_HW_ERR_SOC_FATAL_HBM1_CHNL0},
+ [11] = {"HBM SS1: Channel1", XE_HW_ERR_SOC_FATAL_HBM1_CHNL1},
+ [12] = {"HBM SS1: Channel2", XE_HW_ERR_SOC_FATAL_HBM1_CHNL2},
+ [13] = {"HBM SS1: Channel3", XE_HW_ERR_SOC_FATAL_HBM1_CHNL3},
+ [14] = {"HBM SS1: Channel4", XE_HW_ERR_SOC_FATAL_HBM1_CHNL4},
+ [15] = {"HBM SS1: Channel5", XE_HW_ERR_SOC_FATAL_HBM1_CHNL5},
+ [16] = {"HBM SS1: Channel6", XE_HW_ERR_SOC_FATAL_HBM1_CHNL6},
+ [17] = {"HBM SS1: Channel7", XE_HW_ERR_SOC_FATAL_HBM1_CHNL7},
+ [18] = {"PUNIT", XE_HW_ERR_SOC_FATAL_PUNIT},
+ [19 ... 31] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_glbl_err_reg_fatal[] = {
+ [0] = {"SLAVE LOCAL Reported", XE_HW_ERR_TILE_UNSPEC},
+ [1] = {"HBM SS2: Channel0", XE_HW_ERR_SOC_FATAL_HBM2_CHNL0},
+ [2] = {"HBM SS2: Channel1", XE_HW_ERR_SOC_FATAL_HBM2_CHNL1},
+ [3] = {"HBM SS2: Channel2", XE_HW_ERR_SOC_FATAL_HBM2_CHNL2},
+ [4] = {"HBM SS2: Channel3", XE_HW_ERR_SOC_FATAL_HBM2_CHNL3},
+ [5] = {"HBM SS2: Channel4", XE_HW_ERR_SOC_FATAL_HBM2_CHNL4},
+ [6] = {"HBM SS2: Channel5", XE_HW_ERR_SOC_FATAL_HBM2_CHNL5},
+ [7] = {"HBM SS2: Channel6", XE_HW_ERR_SOC_FATAL_HBM2_CHNL6},
+ [8] = {"HBM SS2: Channel7", XE_HW_ERR_SOC_FATAL_HBM2_CHNL7},
+ [9] = {"HBM SS3: Channel0", XE_HW_ERR_SOC_FATAL_HBM3_CHNL0},
+ [10] = {"HBM SS3: Channel1", XE_HW_ERR_SOC_FATAL_HBM3_CHNL1},
+ [11] = {"HBM SS3: Channel2", XE_HW_ERR_SOC_FATAL_HBM3_CHNL2},
+ [12] = {"HBM SS3: Channel3", XE_HW_ERR_SOC_FATAL_HBM3_CHNL3},
+ [13] = {"HBM SS3: Channel4", XE_HW_ERR_SOC_FATAL_HBM3_CHNL4},
+ [14] = {"HBM SS3: Channel5", XE_HW_ERR_SOC_FATAL_HBM3_CHNL5},
+ [15] = {"HBM SS3: Channel6", XE_HW_ERR_SOC_FATAL_HBM3_CHNL6},
+ [16] = {"HBM SS3: Channel7", XE_HW_ERR_SOC_FATAL_HBM3_CHNL7},
+ [18] = {"ANR MDFI", XE_HW_ERR_SOC_FATAL_ANR_MDFI},
+ [17] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+ [19 ... 31] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_lcl_err_reg_fatal[] = {
+ [0] = {"Local IEH Internal: Malformed PCIe AER", XE_HW_ERR_SOC_FATAL_PCIE_AER},
+ [1] = {"Local IEH Internal: Malformed PCIe ERR", XE_HW_ERR_SOC_FATAL_PCIE_ERR},
+ [2] = {"Local IEH Internal: UR CONDITIONS IN IEH", XE_HW_ERR_SOC_FATAL_UR_COND},
+ [3] = {"Local IEH Internal: FROM SERR SOURCES", XE_HW_ERR_SOC_FATAL_SERR_SRCS},
+ [4 ... 31] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_mstr_lcl_err_reg_fatal[] = {
+ [0 ... 3] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+ [4] = {"Base Die MDFI T2T", XE_HW_ERR_SOC_FATAL_MDFI_T2T},
+ [5] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+ [6] = {"Base Die MDFI T2C", XE_HW_ERR_SOC_FATAL_MDFI_T2C},
+ [7] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+ [8] = {"Invalid CSC PSF Command Parity", XE_HW_ERR_SOC_FATAL_CSC_PSF_CMD},
+ [9] = {"Invalid CSC PSF Unexpected Completion", XE_HW_ERR_SOC_FATAL_CSC_PSF_CMP},
+ [10] = {"Invalid CSC PSF Unsupported Request", XE_HW_ERR_SOC_FATAL_CSC_PSF_REQ},
+ [11] = {"Invalid PCIe PSF Command Parity", XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMD},
+ [12] = {"PCIe PSF Unexpected Completion", XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMP},
+ [13] = {"PCIe PSF Unsupported Request", XE_HW_ERR_SOC_FATAL_PCIE_PSF_REQ},
+ [14 ... 31] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
static void xe_assign_hw_err_regs(struct xe_device *xe)
{
const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
const struct err_name_index_pair **gsc_error = xe->hw_err_regs.gsc_error;
+ const struct err_name_index_pair **soc_mstr_glbl = xe->hw_err_regs.soc_mstr_glbl;
+ const struct err_name_index_pair **soc_mstr_lcl = xe->hw_err_regs.soc_mstr_lcl;
+ const struct err_name_index_pair **soc_slave_glbl = xe->hw_err_regs.soc_slave_glbl;
+ const struct err_name_index_pair **soc_slave_lcl = xe->hw_err_regs.soc_slave_lcl;
/* Error reporting is supported only for DG2 and PVC currently. */
if (xe->info.platform == XE_DG2) {
@@ -217,6 +290,10 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
gsc_error[HARDWARE_ERROR_CORRECTABLE] = pvc_gsc_correctable_err_reg;
gsc_error[HARDWARE_ERROR_NONFATAL] = pvc_gsc_nonfatal_err_reg;
+ soc_mstr_glbl[HARDWARE_ERROR_FATAL] = pvc_soc_mstr_glbl_err_reg_fatal;
+ soc_mstr_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_mstr_lcl_err_reg_fatal;
+ soc_slave_glbl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_glbl_err_reg_fatal;
+ soc_slave_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_lcl_err_reg_fatal;
}
}
@@ -447,6 +524,114 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
xe_mmio_write32(>->tile->mmio, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
}
+static void
+xe_soc_log_err_update_cntr(struct xe_tile *tile, const enum hardware_error hw_err,
+ u32 errbit, const struct err_name_index_pair *reg_info)
+{
+ const char *name;
+ u32 indx;
+
+ const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
+
+ name = reg_info[errbit].name;
+ indx = reg_info[errbit].index;
+
+ drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported SOC %s %s error, bit[%d] is set\n",
+ tile->id, name, hwerr_to_str, errbit);
+
+ if (indx != XE_HW_ERR_TILE_UNSPEC)
+ xe_update_hw_error_cnt(&tile_to_xe(tile)->drm, &tile->errors.hw_error, indx);
+}
+
+static void
+xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+ unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
+ struct hardware_errors_regs *err_regs;
+ u32 errbit, base, slave_base;
+ int i;
+
+ struct xe_gt *gt = tile->primary_gt;
+
+ lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
+
+ if ((tile_to_xe(tile)->info.platform != XE_PVC) || hw_err != HARDWARE_ERROR_FATAL)
+ return;
+
+ base = SOC_PVC_BASE;
+ slave_base = SOC_PVC_SLAVE_BASE;
+ err_regs = &tile_to_xe(tile)->hw_err_regs;
+
+ /*
+ * Mask error type in GSYSEVTCTL so that no new errors of the type
+ * will be reported. Read the master global IEH error register if
+ * BIT 1 is set then process the slave IEH first. If BIT 0 in
+ * global error register is set then process the corresponding
+ * Local error registers
+ */
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
+
+ mst_glb_errstat = xe_mmio_read32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
+ drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
+ tile->id, mst_glb_errstat);
+
+ if (mst_glb_errstat & REG_BIT(SOC_IEH1_GLOBAL_ERR_STATUS)) {
+ slv_glb_errstat = xe_mmio_read32(>->tile->mmio,
+ SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
+ drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
+ tile->id, slv_glb_errstat);
+
+ if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
+ lcl_errstat = xe_mmio_read32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
+ hw_err));
+ drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
+ tile->id, lcl_errstat);
+
+ for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE)
+ xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+ err_regs->soc_slave_lcl[hw_err]);
+
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+ lcl_errstat);
+ }
+
+ for_each_set_bit(errbit, &slv_glb_errstat, XE_RAS_REG_SIZE)
+ xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+ err_regs->soc_slave_glbl[hw_err]);
+
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+ slv_glb_errstat);
+ }
+
+ if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
+ lcl_errstat = xe_mmio_read32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
+ drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
+ tile->id, lcl_errstat);
+
+ for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE)
+ xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+ err_regs->soc_mstr_lcl[hw_err]);
+
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
+ }
+
+ for_each_set_bit(errbit, &mst_glb_errstat, XE_RAS_REG_SIZE)
+ xe_soc_log_err_update_cntr(tile, hw_err, errbit, err_regs->soc_mstr_glbl[hw_err]);
+
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+ mst_glb_errstat);
+
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+ (HARDWARE_ERROR_MAX << 1) + 1);
+}
+
static void
xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
{
@@ -502,6 +687,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
if (errbit == XE_GSC_ERROR)
xe_gsc_hw_error_handler(tile, hw_err);
+
+ if (errbit == XE_SOC_ERROR)
+ xe_soc_hw_error_handler(tile, hw_err);
}
xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), errsrc);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 20036a523963..ecd7edfcd38b 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -12,6 +12,8 @@
#define ERR_STAT_GT_VCTR_LEN (8)
+#define XE_SOC_NUM_IEH 2
+
/* Error categories reported by hardware */
enum hardware_error {
HARDWARE_ERROR_CORRECTABLE = 0,
@@ -51,6 +53,53 @@ enum xe_tile_hw_errors {
XE_HW_ERR_GSC_NONFATAL_SELF_MBIST,
XE_HW_ERR_GSC_NONFATAL_AON_RF_PARITY,
XE_HW_ERR_GSC_NONFATAL_UNKNOWN,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL0,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL1,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL2,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL3,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL4,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL5,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL6,
+ XE_HW_ERR_SOC_FATAL_HBM0_CHNL7,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL0,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL1,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL2,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL3,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL4,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL5,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL6,
+ XE_HW_ERR_SOC_FATAL_HBM1_CHNL7,
+ XE_HW_ERR_SOC_FATAL_PUNIT,
+ XE_HW_ERR_SOC_FATAL_UNKNOWN,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL0,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL1,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL2,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL3,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL4,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL5,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL6,
+ XE_HW_ERR_SOC_FATAL_HBM2_CHNL7,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL0,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL1,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL2,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL3,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL4,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL5,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL6,
+ XE_HW_ERR_SOC_FATAL_HBM3_CHNL7,
+ XE_HW_ERR_SOC_FATAL_ANR_MDFI,
+ XE_HW_ERR_SOC_FATAL_PCIE_AER,
+ XE_HW_ERR_SOC_FATAL_PCIE_ERR,
+ XE_HW_ERR_SOC_FATAL_UR_COND,
+ XE_HW_ERR_SOC_FATAL_SERR_SRCS,
+ XE_HW_ERR_SOC_FATAL_MDFI_T2T,
+ XE_HW_ERR_SOC_FATAL_MDFI_T2C,
+ XE_HW_ERR_SOC_FATAL_CSC_PSF_CMD,
+ XE_HW_ERR_SOC_FATAL_CSC_PSF_CMP,
+ XE_HW_ERR_SOC_FATAL_CSC_PSF_REQ,
+ XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMD,
+ XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMP,
+ XE_HW_ERR_SOC_FATAL_PCIE_PSF_REQ,
};
enum gt_vctr_registers {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 07/10] drm/xe: Support SOC NONFATAL error handling for PVC.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (5 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 06/10] drm/xe: Support SOC FATAL error handling " Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 08/10] drm/xe: Handle MDFI error severity Aravind Iddamsetty
` (6 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Report the SOC nonfatal hardware error and update the counters which
will increment incase of error.
v2
- Use xe_assign_hw_err_regs to initilaize registers.
- Dont use the counters if error is being reported by second level
registers.
- Fix Num of IEH to 2.
- Follow the convention source_typeoferror_errorname for enum and error
reporting.(Aravind)
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/xe_hw_error.c | 70 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_hw_error.h | 39 ++++++++++++++++++
2 files changed, 108 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 927bf2ab401f..705a670f01fc 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -260,6 +260,67 @@ static const struct err_name_index_pair pvc_soc_mstr_lcl_err_reg_fatal[] = {
[14 ... 31] = {"Undefined", XE_HW_ERR_SOC_FATAL_UNKNOWN},
};
+static const struct err_name_index_pair pvc_soc_mstr_glbl_err_reg_nonfatal[] = {
+ [0] = {"MASTER LOCAL Reported", XE_HW_ERR_TILE_UNSPEC},
+ [1] = {"SLAVE GLOBAL Reported", XE_HW_ERR_TILE_UNSPEC},
+ [2] = {"HBM SS0: Channel0", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL0},
+ [3] = {"HBM SS0: Channel1", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL1},
+ [4] = {"HBM SS0: Channel2", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL2},
+ [5] = {"HBM SS0: Channel3", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL3},
+ [6] = {"HBM SS0: Channel4", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL4},
+ [7] = {"HBM SS0: Channel5", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL5},
+ [8] = {"HBM SS0: Channel6", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL6},
+ [9] = {"HBM SS0: Channel7", XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL7},
+ [10] = {"HBM SS1: Channel0", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL0},
+ [11] = {"HBM SS1: Channel1", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL1},
+ [12] = {"HBM SS1: Channel2", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL2},
+ [13] = {"HBM SS1: Channel3", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL3},
+ [14] = {"HBM SS1: Channel4", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL4},
+ [15] = {"HBM SS1: Channel5", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL5},
+ [16] = {"HBM SS1: Channel6", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL6},
+ [17] = {"HBM SS1: Channel7", XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL7},
+ [18 ... 31] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_glbl_err_reg_nonfatal[] = {
+ [0] = {"SLAVE LOCAL Reported", XE_HW_ERR_TILE_UNSPEC},
+ [1] = {"HBM SS2: Channel0", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL0},
+ [2] = {"HBM SS2: Channel1", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL1},
+ [3] = {"HBM SS2: Channel2", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL2},
+ [4] = {"HBM SS2: Channel3", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL3},
+ [5] = {"HBM SS2: Channel4", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL4},
+ [6] = {"HBM SS2: Channel5", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL5},
+ [7] = {"HBM SS2: Channel6", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL6},
+ [8] = {"HBM SS2: Channel7", XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL7},
+ [9] = {"HBM SS3: Channel0", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL0},
+ [10] = {"HBM SS3: Channel1", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL1},
+ [11] = {"HBM SS3: Channel2", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL2},
+ [12] = {"HBM SS3: Channel3", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL3},
+ [13] = {"HBM SS3: Channel4", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL4},
+ [14] = {"HBM SS3: Channel5", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL5},
+ [15] = {"HBM SS3: Channel6", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL6},
+ [16] = {"HBM SS3: Channel7", XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL7},
+ [18] = {"ANR MDFI", XE_HW_ERR_SOC_NONFATAL_ANR_MDFI},
+ [17] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+ [19 ... 31] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_lcl_err_reg_nonfatal[] = {
+ [0 ... 31] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_mstr_lcl_err_reg_nonfatal[] = {
+ [0 ... 3] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+ [4] = {"Base Die MDFI T2T", XE_HW_ERR_SOC_NONFATAL_MDFI_T2T},
+ [5] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+ [6] = {"Base Die MDFI T2C", XE_HW_ERR_SOC_NONFATAL_MDFI_T2C},
+ [7] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+ [8] = {"Invalid CSC PSF Command Parity", XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMD},
+ [9] = {"Invalid CSC PSF Unexpected Completion", XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMP},
+ [10] = {"Invalid CSC PSF Unsupported Request", XE_HW_ERR_SOC_NONFATAL_CSC_PSF_REQ},
+ [11 ... 31] = {"Undefined", XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
static void xe_assign_hw_err_regs(struct xe_device *xe)
{
const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
@@ -294,6 +355,10 @@ static void xe_assign_hw_err_regs(struct xe_device *xe)
soc_mstr_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_mstr_lcl_err_reg_fatal;
soc_slave_glbl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_glbl_err_reg_fatal;
soc_slave_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_lcl_err_reg_fatal;
+ soc_mstr_glbl[HARDWARE_ERROR_NONFATAL] = pvc_soc_mstr_glbl_err_reg_nonfatal;
+ soc_mstr_lcl[HARDWARE_ERROR_NONFATAL] = pvc_soc_mstr_lcl_err_reg_nonfatal;
+ soc_slave_glbl[HARDWARE_ERROR_NONFATAL] = pvc_soc_slave_glbl_err_reg_nonfatal;
+ soc_slave_lcl[HARDWARE_ERROR_NONFATAL] = pvc_soc_slave_lcl_err_reg_nonfatal;
}
}
@@ -556,7 +621,10 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
- if ((tile_to_xe(tile)->info.platform != XE_PVC) || hw_err != HARDWARE_ERROR_FATAL)
+ if (tile_to_xe(tile)->info.platform != XE_PVC)
+ return;
+
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE)
return;
base = SOC_PVC_BASE;
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index ecd7edfcd38b..e43157aae938 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -100,6 +100,45 @@ enum xe_tile_hw_errors {
XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMD,
XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMP,
XE_HW_ERR_SOC_FATAL_PCIE_PSF_REQ,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL0,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL1,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL2,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL3,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL4,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL5,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL6,
+ XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL7,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL0,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL1,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL2,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL3,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL4,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL5,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL6,
+ XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL7,
+ XE_HW_ERR_SOC_NONFATAL_UNKNOWN,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL0,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL1,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL2,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL3,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL4,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL5,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL6,
+ XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL7,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL0,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL1,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL2,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL3,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL4,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL5,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL6,
+ XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL7,
+ XE_HW_ERR_SOC_NONFATAL_ANR_MDFI,
+ XE_HW_ERR_SOC_NONFATAL_MDFI_T2T,
+ XE_HW_ERR_SOC_NONFATAL_MDFI_T2C,
+ XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMD,
+ XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMP,
+ XE_HW_ERR_SOC_NONFATAL_CSC_PSF_REQ,
};
enum gt_vctr_registers {
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 08/10] drm/xe: Handle MDFI error severity.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (6 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 07/10] drm/xe: Support SOC NONFATAL " Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 09/10] drm/xe: Clear SOC CORRECTABLE error registers Aravind Iddamsetty
` (5 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
NONFATAL and FATAL MDFI(T2T/T2C) errors are reported by same IEH
register and bits (Bit 4 and Bit 6 of 0x282280). To determine the
severity read local first error header log register (0x2822b0).
Value 0x00330000 ensures severity is fatal and 0x00310000 is for NONFATAL
errors. This register doesn't need explicit clearing, clearing MDFI
bit in IEH reg will clear this register too. Incase of nonfatal value
being reported by status register in fatal flow don't clean the MDFI IEH
bit and continue. Same needs to be addressed if value read by status
register is fatal in nonfatal flow.
v2
- Add commit message.
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 9 +++++++++
drivers/gpu/drm/xe/xe_hw_error.c | 16 ++++++++++++++--
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 31604138d511..77d397e650e5 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -38,6 +38,8 @@
#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x) XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
(base) + _SOC_LERRUNCSTS : \
(base) + _SOC_LERRCORSTS)
+#define MDFI_T2T 4
+#define MDFI_T2C 6
#define _DEV_ERR_STAT_NONFATAL 0x100178
@@ -50,6 +52,13 @@
#define XE_SOC_ERROR 16
#define SOC_PVC_BASE 0x282000
+
+#define LOCAL_FIRST_IEH_HEADER_LOG_REG XE_REG(0x2822b0)
+#define MDFI_SEVERITY_FATAL 0x00330000
+#define MDFI_SEVERITY_NONFATAL 0x00310000
+#define MDFI_SEVERITY(x) ((x) == HARDWARE_ERROR_FATAL ? \
+ MDFI_SEVERITY_FATAL : \
+ MDFI_SEVERITY_NONFATAL)
#define SOC_PVC_SLAVE_BASE 0x283000
#define PVC_GSC_HECI1_BASE 0x284000
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 705a670f01fc..690b7df7ccba 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -614,7 +614,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
{
unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
struct hardware_errors_regs *err_regs;
- u32 errbit, base, slave_base;
+ u32 errbit, base, slave_base, ieh_header;
int i;
struct xe_gt *gt = tile->primary_gt;
@@ -682,9 +682,21 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
"Tile%d reported SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
tile->id, lcl_errstat);
- for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE)
+ for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE) {
+ if (errbit == MDFI_T2T || errbit == MDFI_T2C) {
+ ieh_header = xe_mmio_read32(>->tile->mmio, LOCAL_FIRST_IEH_HEADER_LOG_REG);
+ drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d LOCAL_FIRST_IEH_HEADER_LOG_REG:0x%08x\n",
+ tile->id, ieh_header);
+
+ if (ieh_header != MDFI_SEVERITY(hw_err)) {
+ lcl_errstat &= ~REG_BIT(errbit);
+ continue;
+ }
+ }
+
xe_soc_log_err_update_cntr(tile, hw_err, errbit,
err_regs->soc_mstr_lcl[hw_err]);
+ }
xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 09/10] drm/xe: Clear SOC CORRECTABLE error registers.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (7 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 08/10] drm/xe: Handle MDFI error severity Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:48 ` [PATCH 10/10] drm/xe: Clear all SoC errors post warm reset Aravind Iddamsetty
` (4 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
PVC doesn't support correctable SOC error reporting, classify them as
Undefined and clear the registers.
v2
- Fix commit message.
- Although the errors are correctable but they are spurious interrupt.
Hence use drm_err instead of drm_warn.(Aravind)
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/xe_hw_error.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 690b7df7ccba..a77779eb6ce8 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -624,13 +624,31 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
if (tile_to_xe(tile)->info.platform != XE_PVC)
return;
- if (hw_err == HARDWARE_ERROR_CORRECTABLE)
- return;
-
base = SOC_PVC_BASE;
slave_base = SOC_PVC_SLAVE_BASE;
err_regs = &tile_to_xe(tile)->hw_err_regs;
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+ ~REG_BIT(hw_err));
+
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+ REG_GENMASK(31, 0));
+
+ drm_err(&tile_to_xe(tile)->drm, HW_ERR
+ "Tile%d reported Undefine SOC CORRECTABLE error.",
+ tile->id);
+
+ goto unmask_gsysevtctl;
+ }
+
/*
* Mask error type in GSYSEVTCTL so that no new errors of the type
* will be reported. Read the master global IEH error register if
@@ -707,6 +725,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
mst_glb_errstat);
+unmask_gsysevtctl:
for (i = 0; i < XE_SOC_NUM_IEH; i++)
xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
(HARDWARE_ERROR_MAX << 1) + 1);
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/10] drm/xe: Clear all SoC errors post warm reset.
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (8 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 09/10] drm/xe: Clear SOC CORRECTABLE error registers Aravind Iddamsetty
@ 2025-07-30 5:48 ` Aravind Iddamsetty
2025-07-30 5:57 ` ✗ CI.checkpatch: warning for Supporting RAS on XE Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Aravind Iddamsetty @ 2025-07-30 5:48 UTC (permalink / raw)
To: intel-xe; +Cc: riana.tauro, rodrigo.vivi, himal.prasad.ghimiray, anshuman.gupta
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
There are scenarios where there are errors being reported from the SoC
uncore to IEH and not propagated to SG unit. Since these errors are not
propagated to SG unit, driver won't be able to clean them as part of
xe_process_hw_error. Hence clear all SoC register post xe_process_hw_error
during the driver load.
v2
- Fix commit message.
v3
- Limit check to PVC.
v4
- Fix check
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/xe_hw_error.c | 41 ++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index a77779eb6ce8..6a7cd59caac1 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -510,6 +510,46 @@ xe_gt_hw_error_log_vector_reg(struct xe_gt *gt, const enum hardware_error hw_err
}
}
+static void xe_clear_all_soc_errors(struct xe_device *xe)
+{
+ enum hardware_error hw_err;
+ u32 base, slave_base;
+ struct xe_tile *tile;
+ struct xe_gt *gt;
+ unsigned int i;
+
+ if (xe->info.platform != XE_PVC)
+ return;
+
+ base = SOC_PVC_BASE;
+ slave_base = SOC_PVC_SLAVE_BASE;
+
+ hw_err = HARDWARE_ERROR_CORRECTABLE;
+
+ for_each_tile(tile, xe, i) {
+ gt = tile->primary_gt;
+
+ while (hw_err < HARDWARE_ERROR_MAX) {
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+ ~REG_BIT(hw_err));
+
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+ REG_GENMASK(31, 0));
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+ REG_GENMASK(31, 0));
+ hw_err++;
+ }
+ for (i = 0; i < XE_SOC_NUM_IEH; i++)
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+ (HARDWARE_ERROR_MAX << 1) + 1);
+ }
+}
+
static void
xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
{
@@ -852,4 +892,5 @@ void xe_init_hw_errors(struct xe_device *xe)
{
xe_assign_hw_err_regs(xe);
xe_process_hw_errors(xe);
+ xe_clear_all_soc_errors(xe);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* ✗ CI.checkpatch: warning for Supporting RAS on XE
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (9 preceding siblings ...)
2025-07-30 5:48 ` [PATCH 10/10] drm/xe: Clear all SoC errors post warm reset Aravind Iddamsetty
@ 2025-07-30 5:57 ` Patchwork
2025-07-30 5:58 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-07-30 5:57 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-xe
== Series Details ==
Series: Supporting RAS on XE
URL : https://patchwork.freedesktop.org/series/152251/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c298eac5978c38dcc62a70c0d73c91765e7cc296
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c594c627ca17d556e5fd8a5d085c093122916705
Author: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Date: Wed Jul 30 11:18:14 2025 +0530
drm/xe: Clear all SoC errors post warm reset.
There are scenarios where there are errors being reported from the SoC
uncore to IEH and not propagated to SG unit. Since these errors are not
propagated to SG unit, driver won't be able to clean them as part of
xe_process_hw_error. Hence clear all SoC register post xe_process_hw_error
during the driver load.
v2
- Fix commit message.
v3
- Limit check to PVC.
v4
- Fix check
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
+ /mt/dim checkpatch 9378b693d04cb60c6d1b13150244c480a7cd2741 drm-intel
9a1d7207f375 drm/xe: Handle errors from various components.
-:91: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#91: FILE: drivers/gpu/drm/xe/regs/xe_regs.h:13:
+#define DEV_PCIEERR_IS_FATAL(x) REG_BIT(x * 4 + 2)
-:97: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 1 checks, 418 lines checked
ce18b1e994f2 drm/xe: Add new helpers to log hardware errrors.
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#25: FILE: drivers/gpu/drm/xe/xe_gt_printk.h:49:
+#define xe_gt_log_hw_err(_gt, _fmt, ...) \
+ drm_err_ratelimited(>_to_xe(_gt)->drm, HW_ERR "GT%d reported " _fmt, \
+ (_gt)->info.id, ##__VA_ARGS__)
-:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_gt' - possible side-effects?
#29: FILE: drivers/gpu/drm/xe/xe_gt_printk.h:53:
+#define xe_gt_log_hw_warn(_gt, _fmt, ...) \
+ drm_warn(>_to_xe(_gt)->drm, HW_ERR "GT%d reported " _fmt, (_gt)->info.id, ##__VA_ARGS__)
total: 0 errors, 0 warnings, 2 checks, 13 lines checked
3050818acb0d drm/xe: Log and count the GT hardware errors.
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 226 lines checked
2457d6639dc0 drm/xe: Support GT hardware error reporting for PVC.
-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'hw_err' may be better as '(hw_err)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/xe/regs/xe_gt_error_regs.h:26:
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+ ERR_STAT_GT_COR_VCTR_REG(x) : \
+ ERR_STAT_GT_FATAL_VCTR_REG(x))
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#54: FILE: drivers/gpu/drm/xe/regs/xe_gt_error_regs.h:26:
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+ ERR_STAT_GT_COR_VCTR_REG(x) : \
+ ERR_STAT_GT_FATAL_VCTR_REG(x))
total: 0 errors, 0 warnings, 2 checks, 241 lines checked
6af1fcff5a4c drm/xe: Support GSC hardware error reporting for PVC.
-:30: CHECK:LINE_SPACING: Please don't use multiple blank lines
#30: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:8:
+
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#33: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:11:
+#define GSC_HEC_ERR_STAT_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _GSC_HEC_CORR_ERR_STATUS, \
+ (base) + _GSC_HEC_UNCOR_ERR_STATUS))
total: 0 errors, 0 warnings, 2 checks, 175 lines checked
23f0917684c9 drm/xe: Support SOC FATAL error handling for PVC.
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#42: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:17:
+#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _SOC_GCOERRSTS, \
+ (base) + _SOC_GNFERRSTS))
-:47: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#47: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:22:
+#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _SOC_GCOERRSTS, \
+ (base) + _SOC_GNFERRSTS))
-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slave_base' may be better as '(slave_base)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:29:
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x) XE_REG(_PICK_EVEN((x), \
+ (base) + _SOC_GSYSEVTCTL, \
+ slave_base + _SOC_GSYSEVTCTL))
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#60: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:35:
+#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x) XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + _SOC_LERRUNCSTS : \
+ (base) + _SOC_LERRCORSTS)
-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#63: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:38:
+#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x) XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+ (base) + _SOC_LERRUNCSTS : \
+ (base) + _SOC_LERRCORSTS)
-:248: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#248: FILE: drivers/gpu/drm/xe/xe_hw_error.c:574:
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
-:250: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#250: FILE: drivers/gpu/drm/xe/xe_hw_error.c:576:
+ mst_glb_errstat = xe_mmio_read32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
-:263: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#263: FILE: drivers/gpu/drm/xe/xe_hw_error.c:589:
+ lcl_errstat = xe_mmio_read32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
-:264: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#264: FILE: drivers/gpu/drm/xe/xe_hw_error.c:590:
+ lcl_errstat = xe_mmio_read32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
+ hw_err));
-:273: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#273: FILE: drivers/gpu/drm/xe/xe_hw_error.c:599:
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
-:286: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#286: FILE: drivers/gpu/drm/xe/xe_hw_error.c:612:
+ lcl_errstat = xe_mmio_read32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
-:295: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#295: FILE: drivers/gpu/drm/xe/xe_hw_error.c:621:
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
total: 0 errors, 6 warnings, 6 checks, 333 lines checked
aab28408ac84 drm/xe: Support SOC NONFATAL error handling for PVC.
1c82b61f7fe4 drm/xe: Handle MDFI error severity.
-:70: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#70: FILE: drivers/gpu/drm/xe/xe_hw_error.c:687:
+ ieh_header = xe_mmio_read32(>->tile->mmio, LOCAL_FIRST_IEH_HEADER_LOG_REG);
total: 0 errors, 1 warnings, 0 checks, 51 lines checked
f4d5ad148f10 drm/xe: Clear SOC CORRECTABLE error registers.
c594c627ca17 drm/xe: Clear all SoC errors post warm reset.
-:54: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#54: FILE: drivers/gpu/drm/xe/xe_hw_error.c:534:
+ xe_mmio_write32(>->tile->mmio, SOC_GSYSEVTCTL_REG(base, slave_base, i),
-:57: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#57: FILE: drivers/gpu/drm/xe/xe_hw_error.c:537:
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
-:59: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#59: FILE: drivers/gpu/drm/xe/xe_hw_error.c:539:
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
-:61: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#61: FILE: drivers/gpu/drm/xe/xe_hw_error.c:541:
+ xe_mmio_write32(>->tile->mmio, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
-:63: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#63: FILE: drivers/gpu/drm/xe/xe_hw_error.c:543:
+ xe_mmio_write32(>->tile->mmio, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
total: 0 errors, 5 warnings, 0 checks, 51 lines checked
^ permalink raw reply [flat|nested] 18+ messages in thread* ✓ CI.KUnit: success for Supporting RAS on XE
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (10 preceding siblings ...)
2025-07-30 5:57 ` ✗ CI.checkpatch: warning for Supporting RAS on XE Patchwork
@ 2025-07-30 5:58 ` Patchwork
2025-07-30 6:59 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-07-30 8:03 ` ✗ Xe.CI.Full: " Patchwork
13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-07-30 5:58 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-xe
== Series Details ==
Series: Supporting RAS on XE
URL : https://patchwork.freedesktop.org/series/152251/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:57:10] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:57:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:57:42] Starting KUnit Kernel (1/1)...
[05:57:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:57:42] ================== guc_buf (11 subtests) ===================
[05:57:42] [PASSED] test_smallest
[05:57:42] [PASSED] test_largest
[05:57:42] [PASSED] test_granular
[05:57:42] [PASSED] test_unique
[05:57:42] [PASSED] test_overlap
[05:57:42] [PASSED] test_reusable
[05:57:42] [PASSED] test_too_big
[05:57:42] [PASSED] test_flush
[05:57:42] [PASSED] test_lookup
[05:57:42] [PASSED] test_data
[05:57:42] [PASSED] test_class
[05:57:42] ===================== [PASSED] guc_buf =====================
[05:57:42] =================== guc_dbm (7 subtests) ===================
[05:57:42] [PASSED] test_empty
[05:57:42] [PASSED] test_default
[05:57:42] ======================== test_size ========================
[05:57:42] [PASSED] 4
[05:57:42] [PASSED] 8
[05:57:42] [PASSED] 32
[05:57:42] [PASSED] 256
[05:57:42] ==================== [PASSED] test_size ====================
[05:57:42] ======================= test_reuse ========================
[05:57:42] [PASSED] 4
[05:57:42] [PASSED] 8
[05:57:42] [PASSED] 32
[05:57:42] [PASSED] 256
[05:57:42] =================== [PASSED] test_reuse ====================
[05:57:42] =================== test_range_overlap ====================
[05:57:42] [PASSED] 4
[05:57:42] [PASSED] 8
[05:57:42] [PASSED] 32
[05:57:42] [PASSED] 256
[05:57:42] =============== [PASSED] test_range_overlap ================
[05:57:42] =================== test_range_compact ====================
[05:57:42] [PASSED] 4
[05:57:42] [PASSED] 8
[05:57:42] [PASSED] 32
[05:57:42] [PASSED] 256
[05:57:42] =============== [PASSED] test_range_compact ================
[05:57:42] ==================== test_range_spare =====================
[05:57:42] [PASSED] 4
[05:57:42] [PASSED] 8
[05:57:42] [PASSED] 32
[05:57:42] [PASSED] 256
[05:57:42] ================ [PASSED] test_range_spare =================
[05:57:42] ===================== [PASSED] guc_dbm =====================
[05:57:42] =================== guc_idm (6 subtests) ===================
[05:57:42] [PASSED] bad_init
[05:57:42] [PASSED] no_init
[05:57:42] [PASSED] init_fini
[05:57:42] [PASSED] check_used
[05:57:42] [PASSED] check_quota
[05:57:42] [PASSED] check_all
[05:57:42] ===================== [PASSED] guc_idm =====================
[05:57:42] ================== no_relay (3 subtests) ===================
[05:57:42] [PASSED] xe_drops_guc2pf_if_not_ready
[05:57:42] [PASSED] xe_drops_guc2vf_if_not_ready
[05:57:42] [PASSED] xe_rejects_send_if_not_ready
[05:57:42] ==================== [PASSED] no_relay =====================
[05:57:42] ================== pf_relay (14 subtests) ==================
[05:57:42] [PASSED] pf_rejects_guc2pf_too_short
[05:57:42] [PASSED] pf_rejects_guc2pf_too_long
[05:57:42] [PASSED] pf_rejects_guc2pf_no_payload
[05:57:42] [PASSED] pf_fails_no_payload
[05:57:42] [PASSED] pf_fails_bad_origin
[05:57:42] [PASSED] pf_fails_bad_type
[05:57:42] [PASSED] pf_txn_reports_error
[05:57:42] [PASSED] pf_txn_sends_pf2guc
[05:57:42] [PASSED] pf_sends_pf2guc
[05:57:42] [SKIPPED] pf_loopback_nop
[05:57:42] [SKIPPED] pf_loopback_echo
[05:57:42] [SKIPPED] pf_loopback_fail
[05:57:42] [SKIPPED] pf_loopback_busy
[05:57:42] [SKIPPED] pf_loopback_retry
[05:57:42] ==================== [PASSED] pf_relay =====================
[05:57:42] ================== vf_relay (3 subtests) ===================
[05:57:42] [PASSED] vf_rejects_guc2vf_too_short
[05:57:42] [PASSED] vf_rejects_guc2vf_too_long
[05:57:42] [PASSED] vf_rejects_guc2vf_no_payload
[05:57:42] ==================== [PASSED] vf_relay =====================
[05:57:42] ===================== lmtt (1 subtest) =====================
[05:57:42] ======================== test_ops =========================
[05:57:42] [PASSED] 2-level
[05:57:42] [PASSED] multi-level
[05:57:42] ==================== [PASSED] test_ops =====================
[05:57:42] ====================== [PASSED] lmtt =======================
[05:57:42] ================= pf_service (11 subtests) =================
[05:57:42] [PASSED] pf_negotiate_any
[05:57:42] [PASSED] pf_negotiate_base_match
[05:57:42] [PASSED] pf_negotiate_base_newer
[05:57:42] [PASSED] pf_negotiate_base_next
[05:57:42] [SKIPPED] pf_negotiate_base_older
[05:57:42] [PASSED] pf_negotiate_base_prev
[05:57:42] [PASSED] pf_negotiate_latest_match
[05:57:42] [PASSED] pf_negotiate_latest_newer
[05:57:42] [PASSED] pf_negotiate_latest_next
[05:57:42] [SKIPPED] pf_negotiate_latest_older
[05:57:42] [SKIPPED] pf_negotiate_latest_prev
[05:57:42] =================== [PASSED] pf_service ====================
[05:57:42] =================== xe_mocs (2 subtests) ===================
[05:57:42] ================ xe_live_mocs_kernel_kunit ================
[05:57:42] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:57:42] ================ xe_live_mocs_reset_kunit =================
[05:57:42] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:57:42] ==================== [SKIPPED] xe_mocs =====================
[05:57:42] ================= xe_migrate (2 subtests) ==================
[05:57:42] ================= xe_migrate_sanity_kunit =================
[05:57:42] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:57:42] ================== xe_validate_ccs_kunit ==================
[05:57:42] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:57:42] =================== [SKIPPED] xe_migrate ===================
[05:57:42] ================== xe_dma_buf (1 subtest) ==================
[05:57:42] ==================== xe_dma_buf_kunit =====================
[05:57:42] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:57:42] =================== [SKIPPED] xe_dma_buf ===================
[05:57:42] ================= xe_bo_shrink (1 subtest) =================
[05:57:42] =================== xe_bo_shrink_kunit ====================
[05:57:42] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:57:42] ================== [SKIPPED] xe_bo_shrink ==================
[05:57:42] ==================== xe_bo (2 subtests) ====================
[05:57:42] ================== xe_ccs_migrate_kunit ===================
[05:57:42] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:57:42] ==================== xe_bo_evict_kunit ====================
[05:57:42] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:57:42] ===================== [SKIPPED] xe_bo ======================
[05:57:42] ==================== args (11 subtests) ====================
[05:57:42] [PASSED] count_args_test
[05:57:42] [PASSED] call_args_example
[05:57:42] [PASSED] call_args_test
[05:57:42] [PASSED] drop_first_arg_example
[05:57:42] [PASSED] drop_first_arg_test
[05:57:42] [PASSED] first_arg_example
[05:57:42] [PASSED] first_arg_test
[05:57:42] [PASSED] last_arg_example
[05:57:42] [PASSED] last_arg_test
[05:57:42] [PASSED] pick_arg_example
[05:57:42] [PASSED] sep_comma_example
[05:57:42] ====================== [PASSED] args =======================
[05:57:42] =================== xe_pci (3 subtests) ====================
[05:57:42] ==================== check_graphics_ip ====================
[05:57:42] [PASSED] 12.70 Xe_LPG
[05:57:42] [PASSED] 12.71 Xe_LPG
[05:57:42] [PASSED] 12.74 Xe_LPG+
[05:57:42] [PASSED] 20.01 Xe2_HPG
[05:57:42] [PASSED] 20.02 Xe2_HPG
[05:57:42] [PASSED] 20.04 Xe2_LPG
[05:57:42] [PASSED] 30.00 Xe3_LPG
[05:57:42] [PASSED] 30.01 Xe3_LPG
[05:57:42] [PASSED] 30.03 Xe3_LPG
[05:57:42] ================ [PASSED] check_graphics_ip ================
[05:57:42] ===================== check_media_ip ======================
[05:57:42] [PASSED] 13.00 Xe_LPM+
[05:57:42] [PASSED] 13.01 Xe2_HPM
[05:57:42] [PASSED] 20.00 Xe2_LPM
[05:57:42] [PASSED] 30.00 Xe3_LPM
[05:57:42] [PASSED] 30.02 Xe3_LPM
[05:57:42] ================= [PASSED] check_media_ip ==================
[05:57:42] ================= check_platform_gt_count =================
[05:57:42] [PASSED] 0x9A60 (TIGERLAKE)
[05:57:42] [PASSED] 0x9A68 (TIGERLAKE)
[05:57:42] [PASSED] 0x9A70 (TIGERLAKE)
[05:57:42] [PASSED] 0x9A40 (TIGERLAKE)
[05:57:42] [PASSED] 0x9A49 (TIGERLAKE)
[05:57:42] [PASSED] 0x9A59 (TIGERLAKE)
[05:57:42] [PASSED] 0x9A78 (TIGERLAKE)
[05:57:42] [PASSED] 0x9AC0 (TIGERLAKE)
[05:57:42] [PASSED] 0x9AC9 (TIGERLAKE)
[05:57:42] [PASSED] 0x9AD9 (TIGERLAKE)
[05:57:42] [PASSED] 0x9AF8 (TIGERLAKE)
[05:57:42] [PASSED] 0x4C80 (ROCKETLAKE)
[05:57:42] [PASSED] 0x4C8A (ROCKETLAKE)
[05:57:42] [PASSED] 0x4C8B (ROCKETLAKE)
[05:57:42] [PASSED] 0x4C8C (ROCKETLAKE)
[05:57:42] [PASSED] 0x4C90 (ROCKETLAKE)
[05:57:42] [PASSED] 0x4C9A (ROCKETLAKE)
[05:57:42] [PASSED] 0x4680 (ALDERLAKE_S)
[05:57:42] [PASSED] 0x4682 (ALDERLAKE_S)
[05:57:42] [PASSED] 0x4688 (ALDERLAKE_S)
[05:57:42] [PASSED] 0x468A (ALDERLAKE_S)
[05:57:42] [PASSED] 0x468B (ALDERLAKE_S)
[05:57:42] [PASSED] 0x4690 (ALDERLAKE_S)
[05:57:42] [PASSED] 0x4692 (ALDERLAKE_S)
[05:57:42] [PASSED] 0x4693 (ALDERLAKE_S)
[05:57:42] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46AA (ALDERLAKE_P)
[05:57:42] [PASSED] 0x462A (ALDERLAKE_P)
[05:57:42] [PASSED] 0x4626 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x4628 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:57:42] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:57:42] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:57:42] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:57:42] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:57:42] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:57:42] [PASSED] 0xA721 (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA720 (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:57:42] [PASSED] 0xA780 (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA781 (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA782 (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA783 (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA788 (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA789 (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA78A (ALDERLAKE_S)
[05:57:42] [PASSED] 0xA78B (ALDERLAKE_S)
[05:57:42] [PASSED] 0x4905 (DG1)
[05:57:42] [PASSED] 0x4906 (DG1)
[05:57:42] [PASSED] 0x4907 (DG1)
[05:57:42] [PASSED] 0x4908 (DG1)
[05:57:42] [PASSED] 0x4909 (DG1)
[05:57:42] [PASSED] 0x56C0 (DG2)
[05:57:42] [PASSED] 0x56C2 (DG2)
[05:57:42] [PASSED] 0x56C1 (DG2)
[05:57:42] [PASSED] 0x7D51 (METEORLAKE)
[05:57:42] [PASSED] 0x7DD1 (METEORLAKE)
[05:57:42] [PASSED] 0x7D41 (METEORLAKE)
[05:57:42] [PASSED] 0x7D67 (METEORLAKE)
[05:57:42] [PASSED] 0xB640 (METEORLAKE)
[05:57:42] [PASSED] 0x56A0 (DG2)
[05:57:42] [PASSED] 0x56A1 (DG2)
[05:57:42] [PASSED] 0x56A2 (DG2)
[05:57:42] [PASSED] 0x56BE (DG2)
[05:57:42] [PASSED] 0x56BF (DG2)
[05:57:42] [PASSED] 0x5690 (DG2)
[05:57:42] [PASSED] 0x5691 (DG2)
[05:57:42] [PASSED] 0x5692 (DG2)
[05:57:42] [PASSED] 0x56A5 (DG2)
[05:57:42] [PASSED] 0x56A6 (DG2)
[05:57:42] [PASSED] 0x56B0 (DG2)
[05:57:42] [PASSED] 0x56B1 (DG2)
[05:57:42] [PASSED] 0x56BA (DG2)
[05:57:42] [PASSED] 0x56BB (DG2)
[05:57:42] [PASSED] 0x56BC (DG2)
[05:57:42] [PASSED] 0x56BD (DG2)
[05:57:42] [PASSED] 0x5693 (DG2)
[05:57:42] [PASSED] 0x5694 (DG2)
[05:57:42] [PASSED] 0x5695 (DG2)
[05:57:42] [PASSED] 0x56A3 (DG2)
[05:57:42] [PASSED] 0x56A4 (DG2)
[05:57:42] [PASSED] 0x56B2 (DG2)
[05:57:42] [PASSED] 0x56B3 (DG2)
[05:57:42] [PASSED] 0x5696 (DG2)
[05:57:42] [PASSED] 0x5697 (DG2)
[05:57:42] [PASSED] 0xB69 (PVC)
[05:57:42] [PASSED] 0xB6E (PVC)
[05:57:42] [PASSED] 0xBD4 (PVC)
[05:57:42] [PASSED] 0xBD5 (PVC)
[05:57:42] [PASSED] 0xBD6 (PVC)
[05:57:42] [PASSED] 0xBD7 (PVC)
[05:57:42] [PASSED] 0xBD8 (PVC)
[05:57:42] [PASSED] 0xBD9 (PVC)
[05:57:42] [PASSED] 0xBDA (PVC)
[05:57:42] [PASSED] 0xBDB (PVC)
[05:57:42] [PASSED] 0xBE0 (PVC)
[05:57:42] [PASSED] 0xBE1 (PVC)
[05:57:42] [PASSED] 0xBE5 (PVC)
[05:57:42] [PASSED] 0x7D40 (METEORLAKE)
[05:57:42] [PASSED] 0x7D45 (METEORLAKE)
[05:57:42] [PASSED] 0x7D55 (METEORLAKE)
[05:57:42] [PASSED] 0x7D60 (METEORLAKE)
[05:57:42] [PASSED] 0x7DD5 (METEORLAKE)
[05:57:42] [PASSED] 0x6420 (LUNARLAKE)
[05:57:42] [PASSED] 0x64A0 (LUNARLAKE)
[05:57:42] [PASSED] 0x64B0 (LUNARLAKE)
[05:57:42] [PASSED] 0xE202 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE209 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE20B (BATTLEMAGE)
[05:57:42] [PASSED] 0xE20C (BATTLEMAGE)
[05:57:42] [PASSED] 0xE20D (BATTLEMAGE)
[05:57:42] [PASSED] 0xE210 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE211 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE212 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE216 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE220 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE221 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE222 (BATTLEMAGE)
[05:57:42] [PASSED] 0xE223 (BATTLEMAGE)
[05:57:42] [PASSED] 0xB080 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB081 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB082 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB083 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB084 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB085 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB086 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB087 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB08F (PANTHERLAKE)
[05:57:42] [PASSED] 0xB090 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:57:42] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:57:42] [PASSED] 0xFD80 (PANTHERLAKE)
[05:57:42] [PASSED] 0xFD81 (PANTHERLAKE)
[05:57:42] ============= [PASSED] check_platform_gt_count =============
[05:57:42] ===================== [PASSED] xe_pci ======================
[05:57:42] =================== xe_rtp (2 subtests) ====================
[05:57:42] =============== xe_rtp_process_to_sr_tests ================
[05:57:42] [PASSED] coalesce-same-reg
[05:57:42] [PASSED] no-match-no-add
[05:57:42] [PASSED] match-or
[05:57:42] [PASSED] match-or-xfail
[05:57:42] [PASSED] no-match-no-add-multiple-rules
[05:57:42] [PASSED] two-regs-two-entries
[05:57:42] [PASSED] clr-one-set-other
[05:57:42] [PASSED] set-field
[05:57:42] [PASSED] conflict-duplicate
[05:57:42] [PASSED] conflict-not-disjoint
[05:57:42] [PASSED] conflict-reg-type
[05:57:42] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:57:42] ================== xe_rtp_process_tests ===================
[05:57:42] [PASSED] active1
[05:57:42] [PASSED] active2
[05:57:42] [PASSED] active-inactive
[05:57:42] [PASSED] inactive-active
[05:57:42] [PASSED] inactive-1st_or_active-inactive
[05:57:42] [PASSED] inactive-2nd_or_active-inactive
[05:57:42] [PASSED] inactive-last_or_active-inactive
[05:57:42] [PASSED] inactive-no_or_active-inactive
[05:57:42] ============== [PASSED] xe_rtp_process_tests ===============
[05:57:42] ===================== [PASSED] xe_rtp ======================
[05:57:42] ==================== xe_wa (1 subtest) =====================
[05:57:42] ======================== xe_wa_gt =========================
[05:57:42] [PASSED] TIGERLAKE (B0)
[05:57:42] [PASSED] DG1 (A0)
[05:57:42] [PASSED] DG1 (B0)
[05:57:42] [PASSED] ALDERLAKE_S (A0)
[05:57:42] [PASSED] ALDERLAKE_S (B0)
[05:57:42] [PASSED] ALDERLAKE_S (C0)
[05:57:42] [PASSED] ALDERLAKE_S (D0)
[05:57:42] [PASSED] ALDERLAKE_P (A0)
[05:57:42] [PASSED] ALDERLAKE_P (B0)
[05:57:42] [PASSED] ALDERLAKE_P (C0)
[05:57:42] [PASSED] ALDERLAKE_S_RPLS (D0)
[05:57:42] [PASSED] ALDERLAKE_P_RPLU (E0)
[05:57:42] [PASSED] DG2_G10 (C0)
[05:57:42] [PASSED] DG2_G11 (B1)
[05:57:42] [PASSED] DG2_G12 (A1)
[05:57:42] [PASSED] METEORLAKE (g:A0, m:A0)
[05:57:42] [PASSED] METEORLAKE (g:A0, m:A0)
[05:57:42] [PASSED] METEORLAKE (g:A0, m:A0)
[05:57:42] [PASSED] LUNARLAKE (g:A0, m:A0)
[05:57:42] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[05:57:42] [PASSED] BATTLEMAGE (g:A0, m:A1)
[05:57:42] ==================== [PASSED] xe_wa_gt =====================
[05:57:42] ====================== [PASSED] xe_wa ======================
[05:57:42] ============================================================
[05:57:42] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[05:57:42] Elapsed time: 31.967s total, 4.247s configuring, 27.403s building, 0.310s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:57:42] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:57:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:58:06] Starting KUnit Kernel (1/1)...
[05:58:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:58:06] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:58:06] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:58:06] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:58:06] =========== drm_validate_clone_mode (2 subtests) ===========
[05:58:06] ============== drm_test_check_in_clone_mode ===============
[05:58:06] [PASSED] in_clone_mode
[05:58:06] [PASSED] not_in_clone_mode
[05:58:06] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:58:06] =============== drm_test_check_valid_clones ===============
[05:58:06] [PASSED] not_in_clone_mode
[05:58:06] [PASSED] valid_clone
[05:58:06] [PASSED] invalid_clone
[05:58:06] =========== [PASSED] drm_test_check_valid_clones ===========
[05:58:06] ============= [PASSED] drm_validate_clone_mode =============
[05:58:06] ============= drm_validate_modeset (1 subtest) =============
[05:58:06] [PASSED] drm_test_check_connector_changed_modeset
[05:58:06] ============== [PASSED] drm_validate_modeset ===============
[05:58:06] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:58:06] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:58:06] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:58:06] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:58:06] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:58:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:58:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:58:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:58:06] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:58:06] ============== drm_bridge_alloc (2 subtests) ===============
[05:58:06] [PASSED] drm_test_drm_bridge_alloc_basic
[05:58:06] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:58:06] ================ [PASSED] drm_bridge_alloc =================
[05:58:06] ================== drm_buddy (7 subtests) ==================
[05:58:06] [PASSED] drm_test_buddy_alloc_limit
[05:58:06] [PASSED] drm_test_buddy_alloc_optimistic
[05:58:06] [PASSED] drm_test_buddy_alloc_pessimistic
[05:58:06] [PASSED] drm_test_buddy_alloc_pathological
[05:58:06] [PASSED] drm_test_buddy_alloc_contiguous
[05:58:06] [PASSED] drm_test_buddy_alloc_clear
[05:58:06] [PASSED] drm_test_buddy_alloc_range_bias
[05:58:06] ==================== [PASSED] drm_buddy ====================
[05:58:06] ============= drm_cmdline_parser (40 subtests) =============
[05:58:06] [PASSED] drm_test_cmdline_force_d_only
[05:58:06] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:58:06] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:58:06] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:58:06] [PASSED] drm_test_cmdline_force_e_only
[05:58:06] [PASSED] drm_test_cmdline_res
[05:58:06] [PASSED] drm_test_cmdline_res_vesa
[05:58:06] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:58:06] [PASSED] drm_test_cmdline_res_rblank
[05:58:06] [PASSED] drm_test_cmdline_res_bpp
[05:58:06] [PASSED] drm_test_cmdline_res_refresh
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:58:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:58:06] [PASSED] drm_test_cmdline_res_margins_force_on
[05:58:06] [PASSED] drm_test_cmdline_res_vesa_margins
[05:58:06] [PASSED] drm_test_cmdline_name
[05:58:06] [PASSED] drm_test_cmdline_name_bpp
[05:58:06] [PASSED] drm_test_cmdline_name_option
[05:58:06] [PASSED] drm_test_cmdline_name_bpp_option
[05:58:06] [PASSED] drm_test_cmdline_rotate_0
[05:58:06] [PASSED] drm_test_cmdline_rotate_90
[05:58:06] [PASSED] drm_test_cmdline_rotate_180
[05:58:06] [PASSED] drm_test_cmdline_rotate_270
[05:58:06] [PASSED] drm_test_cmdline_hmirror
[05:58:06] [PASSED] drm_test_cmdline_vmirror
[05:58:06] [PASSED] drm_test_cmdline_margin_options
[05:58:06] [PASSED] drm_test_cmdline_multiple_options
[05:58:06] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:58:06] [PASSED] drm_test_cmdline_extra_and_option
[05:58:06] [PASSED] drm_test_cmdline_freestanding_options
[05:58:06] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:58:06] [PASSED] drm_test_cmdline_panel_orientation
[05:58:06] ================ drm_test_cmdline_invalid =================
[05:58:06] [PASSED] margin_only
[05:58:06] [PASSED] interlace_only
[05:58:06] [PASSED] res_missing_x
[05:58:06] [PASSED] res_missing_y
[05:58:06] [PASSED] res_bad_y
[05:58:06] [PASSED] res_missing_y_bpp
[05:58:06] [PASSED] res_bad_bpp
[05:58:06] [PASSED] res_bad_refresh
[05:58:06] [PASSED] res_bpp_refresh_force_on_off
[05:58:06] [PASSED] res_invalid_mode
[05:58:06] [PASSED] res_bpp_wrong_place_mode
[05:58:06] [PASSED] name_bpp_refresh
[05:58:06] [PASSED] name_refresh
[05:58:06] [PASSED] name_refresh_wrong_mode
[05:58:06] [PASSED] name_refresh_invalid_mode
[05:58:06] [PASSED] rotate_multiple
[05:58:06] [PASSED] rotate_invalid_val
[05:58:06] [PASSED] rotate_truncated
[05:58:06] [PASSED] invalid_option
[05:58:06] [PASSED] invalid_tv_option
[05:58:06] [PASSED] truncated_tv_option
[05:58:06] ============ [PASSED] drm_test_cmdline_invalid =============
[05:58:06] =============== drm_test_cmdline_tv_options ===============
[05:58:06] [PASSED] NTSC
[05:58:06] [PASSED] NTSC_443
[05:58:06] [PASSED] NTSC_J
[05:58:06] [PASSED] PAL
[05:58:06] [PASSED] PAL_M
[05:58:06] [PASSED] PAL_N
[05:58:06] [PASSED] SECAM
[05:58:06] [PASSED] MONO_525
[05:58:06] [PASSED] MONO_625
[05:58:06] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:58:06] =============== [PASSED] drm_cmdline_parser ================
[05:58:06] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:58:06] [PASSED] drm_test_connector_hdmi_init_valid
[05:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:58:06] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:58:06] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:58:06] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:58:06] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:58:06] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:58:06] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:58:06] [PASSED] supported_formats=0x3 yuv420_allowed=1
[05:58:06] [PASSED] supported_formats=0x3 yuv420_allowed=0
[05:58:06] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:58:06] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:58:06] [PASSED] drm_test_connector_hdmi_init_null_product
[05:58:06] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:58:06] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:58:06] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:58:06] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:58:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:58:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:58:06] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:58:06] ========= drm_test_connector_hdmi_init_type_valid =========
[05:58:06] [PASSED] HDMI-A
[05:58:06] [PASSED] HDMI-B
[05:58:06] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:58:06] ======== drm_test_connector_hdmi_init_type_invalid ========
[05:58:06] [PASSED] Unknown
[05:58:06] [PASSED] VGA
[05:58:06] [PASSED] DVI-I
[05:58:06] [PASSED] DVI-D
[05:58:06] [PASSED] DVI-A
[05:58:06] [PASSED] Composite
[05:58:06] [PASSED] SVIDEO
[05:58:06] [PASSED] LVDS
[05:58:06] [PASSED] Component
[05:58:06] [PASSED] DIN
[05:58:06] [PASSED] DP
[05:58:06] [PASSED] TV
[05:58:06] [PASSED] eDP
[05:58:06] [PASSED] Virtual
[05:58:06] [PASSED] DSI
[05:58:06] [PASSED] DPI
[05:58:06] [PASSED] Writeback
[05:58:06] [PASSED] SPI
[05:58:06] [PASSED] USB
[05:58:06] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:58:06] ============ [PASSED] drmm_connector_hdmi_init =============
[05:58:06] ============= drmm_connector_init (3 subtests) =============
[05:58:06] [PASSED] drm_test_drmm_connector_init
[05:58:06] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:58:06] ========= drm_test_drmm_connector_init_type_valid =========
[05:58:06] [PASSED] Unknown
[05:58:06] [PASSED] VGA
[05:58:06] [PASSED] DVI-I
[05:58:06] [PASSED] DVI-D
[05:58:06] [PASSED] DVI-A
[05:58:06] [PASSED] Composite
[05:58:06] [PASSED] SVIDEO
[05:58:06] [PASSED] LVDS
[05:58:06] [PASSED] Component
[05:58:06] [PASSED] DIN
[05:58:06] [PASSED] DP
[05:58:06] [PASSED] HDMI-A
[05:58:06] [PASSED] HDMI-B
[05:58:06] [PASSED] TV
[05:58:06] [PASSED] eDP
[05:58:06] [PASSED] Virtual
[05:58:06] [PASSED] DSI
[05:58:06] [PASSED] DPI
[05:58:06] [PASSED] Writeback
[05:58:06] [PASSED] SPI
[05:58:06] [PASSED] USB
[05:58:06] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:58:06] =============== [PASSED] drmm_connector_init ===============
[05:58:06] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_init
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:58:06] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[05:58:06] [PASSED] Unknown
[05:58:06] [PASSED] VGA
[05:58:06] [PASSED] DVI-I
[05:58:06] [PASSED] DVI-D
[05:58:06] [PASSED] DVI-A
[05:58:06] [PASSED] Composite
[05:58:06] [PASSED] SVIDEO
[05:58:06] [PASSED] LVDS
[05:58:06] [PASSED] Component
[05:58:06] [PASSED] DIN
[05:58:06] [PASSED] DP
[05:58:06] [PASSED] HDMI-A
[05:58:06] [PASSED] HDMI-B
[05:58:06] [PASSED] TV
[05:58:06] [PASSED] eDP
[05:58:06] [PASSED] Virtual
[05:58:06] [PASSED] DSI
[05:58:06] [PASSED] DPI
[05:58:06] [PASSED] Writeback
[05:58:06] [PASSED] SPI
[05:58:06] [PASSED] USB
[05:58:06] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:58:06] ======== drm_test_drm_connector_dynamic_init_name =========
[05:58:06] [PASSED] Unknown
[05:58:06] [PASSED] VGA
[05:58:06] [PASSED] DVI-I
[05:58:06] [PASSED] DVI-D
[05:58:06] [PASSED] DVI-A
[05:58:06] [PASSED] Composite
[05:58:06] [PASSED] SVIDEO
[05:58:06] [PASSED] LVDS
[05:58:06] [PASSED] Component
[05:58:06] [PASSED] DIN
[05:58:06] [PASSED] DP
[05:58:06] [PASSED] HDMI-A
[05:58:06] [PASSED] HDMI-B
[05:58:06] [PASSED] TV
[05:58:06] [PASSED] eDP
[05:58:06] [PASSED] Virtual
[05:58:06] [PASSED] DSI
[05:58:06] [PASSED] DPI
[05:58:06] [PASSED] Writeback
[05:58:06] [PASSED] SPI
[05:58:06] [PASSED] USB
[05:58:06] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:58:06] =========== [PASSED] drm_connector_dynamic_init ============
[05:58:06] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:58:06] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:58:06] ======= drm_connector_dynamic_register (7 subtests) ========
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:58:06] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:58:06] ========= [PASSED] drm_connector_dynamic_register ==========
[05:58:06] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:58:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:58:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:58:06] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:58:06] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:58:06] ========== drm_test_get_tv_mode_from_name_valid ===========
[05:58:06] [PASSED] NTSC
[05:58:06] [PASSED] NTSC-443
[05:58:06] [PASSED] NTSC-J
[05:58:06] [PASSED] PAL
[05:58:06] [PASSED] PAL-M
[05:58:06] [PASSED] PAL-N
[05:58:06] [PASSED] SECAM
[05:58:06] [PASSED] Mono
[05:58:06] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:58:06] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:58:06] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:58:06] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:58:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:58:06] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[05:58:06] [PASSED] VIC 96
[05:58:06] [PASSED] VIC 97
[05:58:06] [PASSED] VIC 101
[05:58:06] [PASSED] VIC 102
[05:58:06] [PASSED] VIC 106
[05:58:06] [PASSED] VIC 107
[05:58:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:58:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:58:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:58:06] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:58:06] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[05:58:06] [PASSED] Automatic
[05:58:06] [PASSED] Full
[05:58:06] [PASSED] Limited 16:235
[05:58:06] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:58:06] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:58:06] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:58:06] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:58:06] === drm_test_drm_hdmi_connector_get_output_format_name ====
[05:58:06] [PASSED] RGB
[05:58:06] [PASSED] YUV 4:2:0
[05:58:06] [PASSED] YUV 4:2:2
[05:58:06] [PASSED] YUV 4:4:4
[05:58:06] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:58:06] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:58:06] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:58:06] ============= drm_damage_helper (21 subtests) ==============
[05:58:06] [PASSED] drm_test_damage_iter_no_damage
[05:58:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:58:06] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:58:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:58:06] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:58:06] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:58:06] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:58:06] [PASSED] drm_test_damage_iter_simple_damage
[05:58:06] [PASSED] drm_test_damage_iter_single_damage
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:58:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:58:06] [PASSED] drm_test_damage_iter_damage
[05:58:06] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:58:06] [PASSED] drm_test_damage_iter_damage_one_outside
[05:58:06] [PASSED] drm_test_damage_iter_damage_src_moved
[05:58:06] [PASSED] drm_test_damage_iter_damage_not_visible
[05:58:06] ================ [PASSED] drm_damage_helper ================
[05:58:06] ============== drm_dp_mst_helper (3 subtests) ==============
[05:58:06] ============== drm_test_dp_mst_calc_pbn_mode ==============
[05:58:06] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:58:06] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:58:06] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:58:06] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:58:06] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:58:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:58:06] ============== drm_test_dp_mst_calc_pbn_div ===============
[05:58:06] [PASSED] Link rate 2000000 lane count 4
[05:58:06] [PASSED] Link rate 2000000 lane count 2
[05:58:06] [PASSED] Link rate 2000000 lane count 1
[05:58:06] [PASSED] Link rate 1350000 lane count 4
[05:58:06] [PASSED] Link rate 1350000 lane count 2
[05:58:06] [PASSED] Link rate 1350000 lane count 1
[05:58:06] [PASSED] Link rate 1000000 lane count 4
[05:58:06] [PASSED] Link rate 1000000 lane count 2
[05:58:06] [PASSED] Link rate 1000000 lane count 1
[05:58:06] [PASSED] Link rate 810000 lane count 4
[05:58:06] [PASSED] Link rate 810000 lane count 2
[05:58:06] [PASSED] Link rate 810000 lane count 1
[05:58:06] [PASSED] Link rate 540000 lane count 4
[05:58:06] [PASSED] Link rate 540000 lane count 2
[05:58:06] [PASSED] Link rate 540000 lane count 1
[05:58:06] [PASSED] Link rate 270000 lane count 4
[05:58:06] [PASSED] Link rate 270000 lane count 2
[05:58:06] [PASSED] Link rate 270000 lane count 1
[05:58:06] [PASSED] Link rate 162000 lane count 4
[05:58:06] [PASSED] Link rate 162000 lane count 2
[05:58:06] [PASSED] Link rate 162000 lane count 1
[05:58:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:58:06] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[05:58:06] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:58:06] [PASSED] DP_POWER_UP_PHY with port number
[05:58:06] [PASSED] DP_POWER_DOWN_PHY with port number
[05:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:58:06] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:58:06] [PASSED] DP_QUERY_PAYLOAD with port number
[05:58:06] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:58:06] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:58:06] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:58:06] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:58:06] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:58:06] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:58:06] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:58:06] [PASSED] DP_REMOTE_I2C_READ with port number
[05:58:06] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:58:06] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:58:06] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:58:06] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:58:06] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:58:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:58:06] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:58:06] ================ [PASSED] drm_dp_mst_helper ================
[05:58:06] ================== drm_exec (7 subtests) ===================
[05:58:06] [PASSED] sanitycheck
[05:58:06] [PASSED] test_lock
[05:58:06] [PASSED] test_lock_unlock
[05:58:06] [PASSED] test_duplicates
[05:58:06] [PASSED] test_prepare
[05:58:06] [PASSED] test_prepare_array
[05:58:06] [PASSED] test_multiple_loops
[05:58:06] ==================== [PASSED] drm_exec =====================
[05:58:06] =========== drm_format_helper_test (17 subtests) ===========
[05:58:06] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:58:06] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:58:06] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:58:06] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:58:06] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:58:06] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:58:06] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:58:06] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:58:06] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:58:06] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:58:06] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:58:06] ============== drm_test_fb_xrgb8888_to_mono ===============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:58:06] ==================== drm_test_fb_swab =====================
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ================ [PASSED] drm_test_fb_swab =================
[05:58:06] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:58:06] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[05:58:06] [PASSED] single_pixel_source_buffer
[05:58:06] [PASSED] single_pixel_clip_rectangle
[05:58:06] [PASSED] well_known_colors
[05:58:06] [PASSED] destination_pitch
[05:58:06] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:58:06] ================= drm_test_fb_clip_offset =================
[05:58:06] [PASSED] pass through
[05:58:06] [PASSED] horizontal offset
[05:58:06] [PASSED] vertical offset
[05:58:06] [PASSED] horizontal and vertical offset
[05:58:06] [PASSED] horizontal offset (custom pitch)
[05:58:06] [PASSED] vertical offset (custom pitch)
[05:58:06] [PASSED] horizontal and vertical offset (custom pitch)
[05:58:06] ============= [PASSED] drm_test_fb_clip_offset =============
[05:58:06] =================== drm_test_fb_memcpy ====================
[05:58:06] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:58:06] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:58:06] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:58:06] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:58:06] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:58:06] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:58:06] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:58:06] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:58:06] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:58:06] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:58:06] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:58:06] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:58:06] =============== [PASSED] drm_test_fb_memcpy ================
[05:58:06] ============= [PASSED] drm_format_helper_test ==============
[05:58:06] ================= drm_format (18 subtests) =================
[05:58:06] [PASSED] drm_test_format_block_width_invalid
[05:58:06] [PASSED] drm_test_format_block_width_one_plane
[05:58:06] [PASSED] drm_test_format_block_width_two_plane
[05:58:06] [PASSED] drm_test_format_block_width_three_plane
[05:58:06] [PASSED] drm_test_format_block_width_tiled
[05:58:06] [PASSED] drm_test_format_block_height_invalid
[05:58:06] [PASSED] drm_test_format_block_height_one_plane
[05:58:06] [PASSED] drm_test_format_block_height_two_plane
[05:58:06] [PASSED] drm_test_format_block_height_three_plane
[05:58:06] [PASSED] drm_test_format_block_height_tiled
[05:58:06] [PASSED] drm_test_format_min_pitch_invalid
[05:58:06] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:58:06] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:58:06] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:58:06] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:58:06] [PASSED] drm_test_format_min_pitch_two_plane
[05:58:06] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:58:06] [PASSED] drm_test_format_min_pitch_tiled
[05:58:06] =================== [PASSED] drm_format ====================
[05:58:06] ============== drm_framebuffer (10 subtests) ===============
[05:58:06] ========== drm_test_framebuffer_check_src_coords ==========
[05:58:06] [PASSED] Success: source fits into fb
[05:58:06] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:58:06] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:58:06] [PASSED] Fail: overflowing fb with source width
[05:58:06] [PASSED] Fail: overflowing fb with source height
[05:58:06] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:58:06] [PASSED] drm_test_framebuffer_cleanup
[05:58:06] =============== drm_test_framebuffer_create ===============
[05:58:06] [PASSED] ABGR8888 normal sizes
[05:58:06] [PASSED] ABGR8888 max sizes
[05:58:06] [PASSED] ABGR8888 pitch greater than min required
[05:58:06] [PASSED] ABGR8888 pitch less than min required
[05:58:06] [PASSED] ABGR8888 Invalid width
[05:58:06] [PASSED] ABGR8888 Invalid buffer handle
[05:58:06] [PASSED] No pixel format
[05:58:06] [PASSED] ABGR8888 Width 0
[05:58:06] [PASSED] ABGR8888 Height 0
[05:58:06] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:58:06] [PASSED] ABGR8888 Large buffer offset
[05:58:06] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:58:06] [PASSED] ABGR8888 Invalid flag
[05:58:06] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:58:06] [PASSED] ABGR8888 Valid buffer modifier
[05:58:06] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:58:06] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] NV12 Normal sizes
[05:58:06] [PASSED] NV12 Max sizes
[05:58:06] [PASSED] NV12 Invalid pitch
[05:58:06] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:58:06] [PASSED] NV12 different modifier per-plane
[05:58:06] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:58:06] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] NV12 Modifier for inexistent plane
[05:58:06] [PASSED] NV12 Handle for inexistent plane
[05:58:06] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:58:06] [PASSED] YVU420 Normal sizes
[05:58:06] [PASSED] YVU420 Max sizes
[05:58:06] [PASSED] YVU420 Invalid pitch
[05:58:06] [PASSED] YVU420 Different pitches
[05:58:06] [PASSED] YVU420 Different buffer offsets/pitches
[05:58:06] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:58:06] [PASSED] YVU420 Valid modifier
[05:58:06] [PASSED] YVU420 Different modifiers per plane
[05:58:06] [PASSED] YVU420 Modifier for inexistent plane
[05:58:06] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:58:06] [PASSED] X0L2 Normal sizes
[05:58:06] [PASSED] X0L2 Max sizes
[05:58:06] [PASSED] X0L2 Invalid pitch
[05:58:06] [PASSED] X0L2 Pitch greater than minimum required
[05:58:06] [PASSED] X0L2 Handle for inexistent plane
[05:58:06] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:58:06] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:58:06] [PASSED] X0L2 Valid modifier
[05:58:06] [PASSED] X0L2 Modifier for inexistent plane
[05:58:06] =========== [PASSED] drm_test_framebuffer_create ===========
[05:58:06] [PASSED] drm_test_framebuffer_free
[05:58:06] [PASSED] drm_test_framebuffer_init
[05:58:06] [PASSED] drm_test_framebuffer_init_bad_format
[05:58:06] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:58:06] [PASSED] drm_test_framebuffer_lookup
[05:58:06] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:58:06] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:58:06] ================= [PASSED] drm_framebuffer =================
[05:58:06] ================ drm_gem_shmem (8 subtests) ================
[05:58:06] [PASSED] drm_gem_shmem_test_obj_create
[05:58:06] [PASSED] drm_gem_shmem_test_obj_create_private
[05:58:06] [PASSED] drm_gem_shmem_test_pin_pages
[05:58:06] [PASSED] drm_gem_shmem_test_vmap
[05:58:06] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:58:06] [PASSED] drm_gem_shmem_test_get_sg_table
[05:58:06] [PASSED] drm_gem_shmem_test_madvise
[05:58:06] [PASSED] drm_gem_shmem_test_purge
[05:58:06] ================== [PASSED] drm_gem_shmem ==================
[05:58:06] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:58:06] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[05:58:06] [PASSED] Automatic
[05:58:06] [PASSED] Full
[05:58:06] [PASSED] Limited 16:235
[05:58:06] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:58:06] [PASSED] drm_test_check_disable_connector
[05:58:06] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:58:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:58:06] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:58:06] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:58:06] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:58:06] [PASSED] drm_test_check_output_bpc_dvi
[05:58:06] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:58:06] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:58:06] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:58:06] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:58:06] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:58:06] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:58:06] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:58:06] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:58:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:58:06] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:58:06] [PASSED] drm_test_check_broadcast_rgb_value
[05:58:06] [PASSED] drm_test_check_bpc_8_value
[05:58:06] [PASSED] drm_test_check_bpc_10_value
[05:58:06] [PASSED] drm_test_check_bpc_12_value
[05:58:06] [PASSED] drm_test_check_format_value
[05:58:06] [PASSED] drm_test_check_tmds_char_value
[05:58:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:58:06] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:58:06] [PASSED] drm_test_check_mode_valid
[05:58:06] [PASSED] drm_test_check_mode_valid_reject
[05:58:06] [PASSED] drm_test_check_mode_valid_reject_rate
[05:58:06] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:58:06] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:58:06] ================= drm_managed (2 subtests) =================
[05:58:06] [PASSED] drm_test_managed_release_action
[05:58:06] [PASSED] drm_test_managed_run_action
[05:58:06] =================== [PASSED] drm_managed ===================
[05:58:06] =================== drm_mm (6 subtests) ====================
[05:58:06] [PASSED] drm_test_mm_init
[05:58:06] [PASSED] drm_test_mm_debug
[05:58:06] [PASSED] drm_test_mm_align32
[05:58:06] [PASSED] drm_test_mm_align64
[05:58:06] [PASSED] drm_test_mm_lowest
[05:58:06] [PASSED] drm_test_mm_highest
[05:58:06] ===================== [PASSED] drm_mm ======================
[05:58:06] ============= drm_modes_analog_tv (5 subtests) =============
[05:58:06] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:58:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:58:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:58:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:58:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:58:06] =============== [PASSED] drm_modes_analog_tv ===============
[05:58:06] ============== drm_plane_helper (2 subtests) ===============
[05:58:06] =============== drm_test_check_plane_state ================
[05:58:06] [PASSED] clipping_simple
[05:58:06] [PASSED] clipping_rotate_reflect
[05:58:06] [PASSED] positioning_simple
[05:58:06] [PASSED] upscaling
[05:58:06] [PASSED] downscaling
[05:58:06] [PASSED] rounding1
[05:58:06] [PASSED] rounding2
[05:58:06] [PASSED] rounding3
[05:58:06] [PASSED] rounding4
[05:58:06] =========== [PASSED] drm_test_check_plane_state ============
[05:58:06] =========== drm_test_check_invalid_plane_state ============
[05:58:06] [PASSED] positioning_invalid
[05:58:06] [PASSED] upscaling_invalid
[05:58:06] [PASSED] downscaling_invalid
[05:58:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:58:06] ================ [PASSED] drm_plane_helper =================
[05:58:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:58:06] ====== drm_test_connector_helper_tv_get_modes_check =======
[05:58:06] [PASSED] None
[05:58:06] [PASSED] PAL
[05:58:06] [PASSED] NTSC
[05:58:06] [PASSED] Both, NTSC Default
[05:58:06] [PASSED] Both, PAL Default
[05:58:06] [PASSED] Both, NTSC Default, with PAL on command-line
[05:58:06] [PASSED] Both, PAL Default, with NTSC on command-line
[05:58:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:58:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:58:06] ================== drm_rect (9 subtests) ===================
[05:58:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:58:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:58:06] [PASSED] drm_test_rect_clip_scaled_clipped
[05:58:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:58:06] ================= drm_test_rect_intersect =================
[05:58:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:58:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:58:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:58:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:58:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:58:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:58:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:58:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:58:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:58:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:58:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:58:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:58:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:58:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:58:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:58:06] ============= [PASSED] drm_test_rect_intersect =============
[05:58:06] ================ drm_test_rect_calc_hscale ================
[05:58:06] [PASSED] normal use
[05:58:06] [PASSED] out of max range
[05:58:06] [PASSED] out of min range
[05:58:06] [PASSED] zero dst
[05:58:06] [PASSED] negative src
[05:58:06] [PASSED] negative dst
[05:58:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:58:06] ================ drm_test_rect_calc_vscale ================
[05:58:06] [PASSED] normal use
[05:58:06] [PASSED] out of max range
[05:58:06] [PASSED] out of min range
[05:58:06] [PASSED] zero dst
[05:58:06] [PASSED] negative src
[05:58:06] [PASSED] negative dst
[05:58:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:58:06] ================== drm_test_rect_rotate ===================
[05:58:06] [PASSED] reflect-x
[05:58:06] [PASSED] reflect-y
[05:58:06] [PASSED] rotate-0
[05:58:06] [PASSED] rotate-90
[05:58:06] [PASSED] rotate-180
[05:58:06] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[05:58:06] ============== [PASSED] drm_test_rect_rotate ===============
[05:58:06] ================ drm_test_rect_rotate_inv =================
[05:58:06] [PASSED] reflect-x
[05:58:06] [PASSED] reflect-y
[05:58:06] [PASSED] rotate-0
[05:58:06] [PASSED] rotate-90
[05:58:06] [PASSED] rotate-180
[05:58:06] [PASSED] rotate-270
[05:58:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:58:06] ==================== [PASSED] drm_rect =====================
[05:58:06] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:58:06] ============ drm_test_sysfb_build_fourcc_list =============
[05:58:06] [PASSED] no native formats
[05:58:06] [PASSED] XRGB8888 as native format
[05:58:06] [PASSED] remove duplicates
[05:58:06] [PASSED] convert alpha formats
[05:58:06] [PASSED] random formats
[05:58:06] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:58:06] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:58:06] ============================================================
[05:58:06] Testing complete. Ran 616 tests: passed: 616
[05:58:06] Elapsed time: 23.738s total, 1.661s configuring, 21.861s building, 0.177s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:58:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:58:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:58:15] Starting KUnit Kernel (1/1)...
[05:58:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:58:15] ================= ttm_device (5 subtests) ==================
[05:58:15] [PASSED] ttm_device_init_basic
[05:58:15] [PASSED] ttm_device_init_multiple
[05:58:15] [PASSED] ttm_device_fini_basic
[05:58:15] [PASSED] ttm_device_init_no_vma_man
[05:58:15] ================== ttm_device_init_pools ==================
[05:58:15] [PASSED] No DMA allocations, no DMA32 required
[05:58:15] [PASSED] DMA allocations, DMA32 required
[05:58:15] [PASSED] No DMA allocations, DMA32 required
[05:58:15] [PASSED] DMA allocations, no DMA32 required
[05:58:15] ============== [PASSED] ttm_device_init_pools ==============
[05:58:15] =================== [PASSED] ttm_device ====================
[05:58:15] ================== ttm_pool (8 subtests) ===================
[05:58:15] ================== ttm_pool_alloc_basic ===================
[05:58:15] [PASSED] One page
[05:58:15] [PASSED] More than one page
[05:58:15] [PASSED] Above the allocation limit
[05:58:15] [PASSED] One page, with coherent DMA mappings enabled
[05:58:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:58:15] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:58:15] ============== ttm_pool_alloc_basic_dma_addr ==============
[05:58:15] [PASSED] One page
[05:58:15] [PASSED] More than one page
[05:58:15] [PASSED] Above the allocation limit
[05:58:15] [PASSED] One page, with coherent DMA mappings enabled
[05:58:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:58:15] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:58:15] [PASSED] ttm_pool_alloc_order_caching_match
[05:58:15] [PASSED] ttm_pool_alloc_caching_mismatch
[05:58:15] [PASSED] ttm_pool_alloc_order_mismatch
[05:58:15] [PASSED] ttm_pool_free_dma_alloc
[05:58:15] [PASSED] ttm_pool_free_no_dma_alloc
[05:58:15] [PASSED] ttm_pool_fini_basic
[05:58:15] ==================== [PASSED] ttm_pool =====================
[05:58:15] ================ ttm_resource (8 subtests) =================
[05:58:15] ================= ttm_resource_init_basic =================
[05:58:15] [PASSED] Init resource in TTM_PL_SYSTEM
[05:58:15] [PASSED] Init resource in TTM_PL_VRAM
[05:58:15] [PASSED] Init resource in a private placement
[05:58:15] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:58:15] ============= [PASSED] ttm_resource_init_basic =============
[05:58:15] [PASSED] ttm_resource_init_pinned
[05:58:15] [PASSED] ttm_resource_fini_basic
[05:58:15] [PASSED] ttm_resource_manager_init_basic
[05:58:15] [PASSED] ttm_resource_manager_usage_basic
[05:58:15] [PASSED] ttm_resource_manager_set_used_basic
[05:58:15] [PASSED] ttm_sys_man_alloc_basic
[05:58:15] [PASSED] ttm_sys_man_free_basic
[05:58:15] ================== [PASSED] ttm_resource ===================
[05:58:15] =================== ttm_tt (15 subtests) ===================
[05:58:15] ==================== ttm_tt_init_basic ====================
[05:58:15] [PASSED] Page-aligned size
[05:58:15] [PASSED] Extra pages requested
[05:58:15] ================ [PASSED] ttm_tt_init_basic ================
[05:58:15] [PASSED] ttm_tt_init_misaligned
[05:58:15] [PASSED] ttm_tt_fini_basic
[05:58:15] [PASSED] ttm_tt_fini_sg
[05:58:15] [PASSED] ttm_tt_fini_shmem
[05:58:15] [PASSED] ttm_tt_create_basic
[05:58:15] [PASSED] ttm_tt_create_invalid_bo_type
[05:58:15] [PASSED] ttm_tt_create_ttm_exists
[05:58:15] [PASSED] ttm_tt_create_failed
[05:58:15] [PASSED] ttm_tt_destroy_basic
[05:58:15] [PASSED] ttm_tt_populate_null_ttm
[05:58:15] [PASSED] ttm_tt_populate_populated_ttm
[05:58:15] [PASSED] ttm_tt_unpopulate_basic
[05:58:15] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:58:15] [PASSED] ttm_tt_swapin_basic
[05:58:15] ===================== [PASSED] ttm_tt ======================
[05:58:15] =================== ttm_bo (14 subtests) ===================
[05:58:15] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[05:58:15] [PASSED] Cannot be interrupted and sleeps
[05:58:15] [PASSED] Cannot be interrupted, locks straight away
[05:58:15] [PASSED] Can be interrupted, sleeps
[05:58:15] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:58:15] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:58:15] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:58:15] [PASSED] ttm_bo_reserve_double_resv
[05:58:15] [PASSED] ttm_bo_reserve_interrupted
[05:58:15] [PASSED] ttm_bo_reserve_deadlock
[05:58:15] [PASSED] ttm_bo_unreserve_basic
[05:58:15] [PASSED] ttm_bo_unreserve_pinned
[05:58:15] [PASSED] ttm_bo_unreserve_bulk
[05:58:15] [PASSED] ttm_bo_put_basic
[05:58:15] [PASSED] ttm_bo_put_shared_resv
[05:58:15] [PASSED] ttm_bo_pin_basic
[05:58:15] [PASSED] ttm_bo_pin_unpin_resource
[05:58:15] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:58:15] ===================== [PASSED] ttm_bo ======================
[05:58:15] ============== ttm_bo_validate (21 subtests) ===============
[05:58:15] ============== ttm_bo_init_reserved_sys_man ===============
[05:58:15] [PASSED] Buffer object for userspace
[05:58:15] [PASSED] Kernel buffer object
[05:58:15] [PASSED] Shared buffer object
[05:58:15] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:58:15] ============== ttm_bo_init_reserved_mock_man ==============
[05:58:15] [PASSED] Buffer object for userspace
[05:58:15] [PASSED] Kernel buffer object
[05:58:15] [PASSED] Shared buffer object
[05:58:15] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:58:15] [PASSED] ttm_bo_init_reserved_resv
[05:58:15] ================== ttm_bo_validate_basic ==================
[05:58:15] [PASSED] Buffer object for userspace
[05:58:15] [PASSED] Kernel buffer object
[05:58:15] [PASSED] Shared buffer object
[05:58:15] ============== [PASSED] ttm_bo_validate_basic ==============
[05:58:15] [PASSED] ttm_bo_validate_invalid_placement
[05:58:15] ============= ttm_bo_validate_same_placement ==============
[05:58:15] [PASSED] System manager
[05:58:15] [PASSED] VRAM manager
[05:58:15] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:58:15] [PASSED] ttm_bo_validate_failed_alloc
[05:58:15] [PASSED] ttm_bo_validate_pinned
[05:58:15] [PASSED] ttm_bo_validate_busy_placement
[05:58:15] ================ ttm_bo_validate_multihop =================
[05:58:15] [PASSED] Buffer object for userspace
[05:58:15] [PASSED] Kernel buffer object
[05:58:15] [PASSED] Shared buffer object
[05:58:15] ============ [PASSED] ttm_bo_validate_multihop =============
[05:58:15] ========== ttm_bo_validate_no_placement_signaled ==========
[05:58:15] [PASSED] Buffer object in system domain, no page vector
[05:58:15] [PASSED] Buffer object in system domain with an existing page vector
[05:58:15] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:58:15] ======== ttm_bo_validate_no_placement_not_signaled ========
[05:58:15] [PASSED] Buffer object for userspace
[05:58:15] [PASSED] Kernel buffer object
[05:58:15] [PASSED] Shared buffer object
[05:58:15] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:58:15] [PASSED] ttm_bo_validate_move_fence_signaled
[05:58:16] ========= ttm_bo_validate_move_fence_not_signaled =========
[05:58:16] [PASSED] Waits for GPU
[05:58:16] [PASSED] Tries to lock straight away
[05:58:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:58:16] [PASSED] ttm_bo_validate_happy_evict
[05:58:16] [PASSED] ttm_bo_validate_all_pinned_evict
[05:58:16] [PASSED] ttm_bo_validate_allowed_only_evict
[05:58:16] [PASSED] ttm_bo_validate_deleted_evict
[05:58:16] [PASSED] ttm_bo_validate_busy_domain_evict
[05:58:16] [PASSED] ttm_bo_validate_evict_gutting
[05:58:16] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:58:16] ================= [PASSED] ttm_bo_validate =================
[05:58:16] ============================================================
[05:58:16] Testing complete. Ran 101 tests: passed: 101
[05:58:16] Elapsed time: 9.562s total, 1.650s configuring, 7.695s building, 0.183s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 18+ messages in thread* ✗ Xe.CI.BAT: failure for Supporting RAS on XE
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (11 preceding siblings ...)
2025-07-30 5:58 ` ✓ CI.KUnit: success " Patchwork
@ 2025-07-30 6:59 ` Patchwork
2025-07-30 8:03 ` ✗ Xe.CI.Full: " Patchwork
13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-07-30 6:59 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2228 bytes --]
== Series Details ==
Series: Supporting RAS on XE
URL : https://patchwork.freedesktop.org/series/152251/
State : failure
== Summary ==
CI Bug Log - changes from xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678_BAT -> xe-pw-152251v1_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-152251v1_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-152251v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (8 -> 7)
------------------------------
Missing (1): bat-adlp-vm
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-152251v1_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@sriov_basic@enable-vfs-autoprobe-on:
- bat-adlp-7: [PASS][1] -> [ABORT][2] +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/bat-adlp-7/igt@sriov_basic@enable-vfs-autoprobe-on.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/bat-adlp-7/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1:
- bat-atsm-2: [PASS][3] -> [ABORT][4] +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/bat-atsm-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/bat-atsm-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
Build changes
-------------
* Linux: xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678 -> xe-pw-152251v1
IGT_8478: 3e7c2bd685397f852853878aef4d9c1e4889a28b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678: b6a72d53a8082ee6ef701042e7cb8a93d6a2b678
xe-pw-152251v1: 152251v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/index.html
[-- Attachment #2: Type: text/html, Size: 2854 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread* ✗ Xe.CI.Full: failure for Supporting RAS on XE
2025-07-30 5:48 [PATCH 00/10] Supporting RAS on XE Aravind Iddamsetty
` (12 preceding siblings ...)
2025-07-30 6:59 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-07-30 8:03 ` Patchwork
13 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-07-30 8:03 UTC (permalink / raw)
To: Aravind Iddamsetty; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 68158 bytes --]
== Series Details ==
Series: Supporting RAS on XE
URL : https://patchwork.freedesktop.org/series/152251/
State : failure
== Summary ==
CI Bug Log - changes from xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678_FULL -> xe-pw-152251v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-152251v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-152251v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-152251v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a2:
- shard-dg2-set2: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-432/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a2.html
* igt@kms_flip@wf_vblank-ts-check@a-hdmi-a2:
- shard-dg2-set2: [PASS][2] -> [FAIL][3] +2 other tests fail
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-432/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a2.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-432/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a2.html
* igt@xe_pmu@engine-activity-most-load-idle:
- shard-adlp: [PASS][4] -> [ABORT][5] +18 other tests abort
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-adlp-8/igt@xe_pmu@engine-activity-most-load-idle.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-adlp-4/igt@xe_pmu@engine-activity-most-load-idle.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@xe_pmu@engine-activity-render-node-idle}:
- shard-adlp: [PASS][6] -> [ABORT][7] +11 other tests abort
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-adlp-6/igt@xe_pmu@engine-activity-render-node-idle.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-adlp-9/igt@xe_pmu@engine-activity-render-node-idle.html
Known issues
------------
Here are the changes found in xe-pw-152251v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_getversion@basic:
- shard-bmg: [PASS][8] -> [FAIL][9] ([Intel XE#4672])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@core_getversion@basic.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@core_getversion@basic.html
* igt@core_hotunplug@hotreplug-lateclose:
- shard-bmg: [PASS][10] -> [SKIP][11] ([Intel XE#4963])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@core_hotunplug@hotreplug-lateclose.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@core_hotunplug@hotreplug-lateclose.html
* igt@fbdev@info:
- shard-bmg: [PASS][12] -> [SKIP][13] ([Intel XE#2134])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@fbdev@info.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@fbdev@info.html
* igt@kms_addfb_basic@size-max:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#4950]) +7 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_addfb_basic@size-max.html
* igt@kms_big_fb@linear-8bpp-rotate-180:
- shard-bmg: [PASS][15] -> [SKIP][16] ([Intel XE#4947]) +20 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_big_fb@linear-8bpp-rotate-180.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_big_fb@linear-8bpp-rotate-180.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#787]) +132 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#455] / [Intel XE#787]) +18 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-dp-2.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][20] ([Intel XE#1178]) +1 other test fail
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][21] ([Intel XE#1188])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-7/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-bmg: [PASS][22] -> [SKIP][23] ([Intel XE#2291]) +4 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#4494] / [i915#3804])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-463/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [PASS][25] -> [SKIP][26] ([Intel XE#4354])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-3/igt@kms_dp_link_training@non-uhbr-sst.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [PASS][27] -> [FAIL][28] ([Intel XE#301] / [Intel XE#3149])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [PASS][29] -> [FAIL][30] ([Intel XE#301]) +2 other tests fail
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a6:
- shard-dg2-set2: [PASS][31] -> [FAIL][32] ([Intel XE#301]) +1 other test fail
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a6.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a6.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-bmg: [PASS][33] -> [INCOMPLETE][34] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2293]) +3 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#4947]) +6 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_lease@setcrtc-implicit-plane:
- shard-bmg: [PASS][37] -> [SKIP][38] ([Intel XE#4950]) +69 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_lease@setcrtc-implicit-plane.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_lease@setcrtc-implicit-plane.html
* igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-2-size-64:
- shard-dg2-set2: NOTRUN -> [FAIL][39] ([Intel XE#616])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-432/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-2-size-64.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2763]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
* igt@kms_pm_rpm@i2c:
- shard-bmg: [PASS][41] -> [SKIP][42] ([Intel XE#4962]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_pm_rpm@i2c.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_pm_rpm@i2c.html
* igt@xe_exec_basic@many-bindexecqueue-rebind:
- shard-bmg: [PASS][43] -> [SKIP][44] ([Intel XE#4945]) +387 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@xe_exec_basic@many-bindexecqueue-rebind.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_exec_basic@many-bindexecqueue-rebind.html
* igt@xe_exec_basic@many-null-defer-bind:
- shard-dg2-set2: [PASS][45] -> [DMESG-FAIL][46] ([Intel XE#5213])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-433/igt@xe_exec_basic@many-null-defer-bind.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-436/igt@xe_exec_basic@many-null-defer-bind.html
* igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
- shard-dg2-set2: [PASS][47] -> [SKIP][48] ([Intel XE#1392]) +5 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-434/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
* igt@xe_exec_system_allocator@threads-many-execqueues-free-nomemset:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#4945]) +24 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-execqueues-free-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
- shard-lnl: [PASS][50] -> [FAIL][51] ([Intel XE#5018]) +1 other test fail
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
* igt@xe_module_load@many-reload:
- shard-bmg: [PASS][52] -> [FAIL][53] ([Intel XE#5679])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@xe_module_load@many-reload.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_module_load@many-reload.html
* igt@xe_pm@s2idle-basic-exec:
- shard-adlp: [PASS][54] -> [DMESG-WARN][55] ([Intel XE#2953] / [Intel XE#4173]) +9 other tests dmesg-warn
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-adlp-3/igt@xe_pm@s2idle-basic-exec.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-adlp-3/igt@xe_pm@s2idle-basic-exec.html
#### Possible fixes ####
* igt@core_hotunplug@hotreplug:
- shard-bmg: [SKIP][56] ([Intel XE#4963]) -> [PASS][57] +2 other tests pass
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@core_hotunplug@hotreplug.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@core_hotunplug@hotreplug.html
* igt@kms_big_fb@linear-16bpp-rotate-180:
- shard-bmg: [SKIP][58] ([Intel XE#4947]) -> [PASS][59] +12 other tests pass
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_big_fb@linear-16bpp-rotate-180.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_big_fb@linear-16bpp-rotate-180.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-bmg: [SKIP][60] ([Intel XE#2291]) -> [PASS][61] +2 other tests pass
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-bmg: [SKIP][62] ([Intel XE#1340]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [SKIP][64] ([Intel XE#2316]) -> [PASS][65] +1 other test pass
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@blocking-absolute-wf_vblank-interruptible:
- shard-adlp: [DMESG-WARN][66] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][67] +1 other test pass
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-adlp-4/igt@kms_flip@blocking-absolute-wf_vblank-interruptible.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-adlp-3/igt@kms_flip@blocking-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-panning-vs-hang:
- shard-bmg: [SKIP][68] ([Intel XE#4950]) -> [PASS][69] +68 other tests pass
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_flip@flip-vs-panning-vs-hang.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_flip@flip-vs-panning-vs-hang.html
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-adlp: [DMESG-WARN][70] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-adlp-4/igt@kms_flip@flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][72] ([Intel XE#4543]) -> [PASS][73] +2 other tests pass
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-adlp-4/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-bmg: [SKIP][74] ([Intel XE#4962]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_pm_rpm@modeset-non-lpsp.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@xe_exec_basic@multigpu-once-null:
- shard-dg2-set2: [SKIP][76] ([Intel XE#1392]) -> [PASS][77] +6 other tests pass
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-433/igt@xe_exec_basic@multigpu-once-null.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-bmg: [DMESG-WARN][78] ([Intel XE#3876]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-4/igt@xe_exec_reset@parallel-gt-reset.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_system_allocator@threads-many-large-new:
- shard-bmg: [SKIP][80] ([Intel XE#4945]) -> [PASS][81] +305 other tests pass
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-large-new.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-large-new.html
* igt@xe_module_load@reload:
- shard-bmg: [FAIL][82] ([Intel XE#5679]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_module_load@reload.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@xe_module_load@reload.html
* igt@xe_pmu@gt-frequency:
- shard-dg2-set2: [FAIL][84] ([Intel XE#5166]) -> [PASS][85] +1 other test pass
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-432/igt@xe_pmu@gt-frequency.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-433/igt@xe_pmu@gt-frequency.html
#### Warnings ####
* igt@kms_async_flips@invalid-async-flip:
- shard-bmg: [SKIP][86] ([Intel XE#4950]) -> [SKIP][87] ([Intel XE#873])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_async_flips@invalid-async-flip.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-bmg: [SKIP][88] ([Intel XE#3768]) -> [SKIP][89] ([Intel XE#4950])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_async_flips@invalid-async-flip-atomic.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_async_flips@invalid-async-flip-atomic.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-bmg: [SKIP][90] ([Intel XE#2327]) -> [SKIP][91] ([Intel XE#4947]) +2 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-bmg: [SKIP][92] ([Intel XE#4947]) -> [SKIP][93] ([Intel XE#2327]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-bmg: [SKIP][94] ([Intel XE#4947]) -> [SKIP][95] ([Intel XE#1124]) +7 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-bmg: [SKIP][96] ([Intel XE#2328]) -> [SKIP][97] ([Intel XE#4947])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-bmg: [SKIP][98] ([Intel XE#1124]) -> [SKIP][99] ([Intel XE#4947]) +7 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
- shard-bmg: [SKIP][100] ([Intel XE#2314] / [Intel XE#2894]) -> [SKIP][101] ([Intel XE#4950])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-bmg: [SKIP][102] ([Intel XE#4950]) -> [SKIP][103] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-4-displays-2160x1440p:
- shard-bmg: [SKIP][104] ([Intel XE#4950]) -> [SKIP][105] ([Intel XE#367])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-4-displays-3840x2160p:
- shard-bmg: [SKIP][106] ([Intel XE#367]) -> [SKIP][107] ([Intel XE#4950]) +3 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-bmg: [SKIP][108] ([Intel XE#2652] / [Intel XE#787]) -> [SKIP][109] ([Intel XE#4947]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
- shard-bmg: [SKIP][110] ([Intel XE#4947]) -> [SKIP][111] ([Intel XE#2887]) +11 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
- shard-bmg: [SKIP][112] ([Intel XE#2887]) -> [SKIP][113] ([Intel XE#4947]) +10 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
- shard-bmg: [SKIP][114] ([Intel XE#3432]) -> [SKIP][115] ([Intel XE#4947]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-bmg: [SKIP][116] ([Intel XE#4947]) -> [SKIP][117] ([Intel XE#2652] / [Intel XE#787])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_cdclk@plane-scaling:
- shard-bmg: [SKIP][118] ([Intel XE#2724]) -> [SKIP][119] ([Intel XE#4947]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_cdclk@plane-scaling.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-bmg: [SKIP][120] ([Intel XE#4950]) -> [SKIP][121] ([Intel XE#2325]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_chamelium_color@ctm-0-50.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_color@degamma:
- shard-bmg: [SKIP][122] ([Intel XE#2325]) -> [SKIP][123] ([Intel XE#4950])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_chamelium_color@degamma.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-bmg: [SKIP][124] ([Intel XE#2252]) -> [SKIP][125] ([Intel XE#4950]) +6 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-bmg: [SKIP][126] ([Intel XE#4950]) -> [SKIP][127] ([Intel XE#2252]) +7 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_chamelium_hpd@vga-hpd-fast.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@legacy:
- shard-bmg: [FAIL][128] ([Intel XE#1178]) -> [SKIP][129] ([Intel XE#2341])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-3/igt@kms_content_protection@legacy.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm:
- shard-bmg: [SKIP][130] ([Intel XE#4950]) -> [FAIL][131] ([Intel XE#1178]) +1 other test fail
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_content_protection@srm.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-bmg: [SKIP][132] ([Intel XE#2341]) -> [FAIL][133] ([Intel XE#1188])
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_content_protection@uevent.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-bmg: [SKIP][134] ([Intel XE#2321]) -> [SKIP][135] ([Intel XE#4950]) +1 other test skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_cursor_crc@cursor-onscreen-512x170.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-bmg: [SKIP][136] ([Intel XE#2320]) -> [SKIP][137] ([Intel XE#4950]) +4 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@kms_cursor_crc@cursor-random-32x32.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-bmg: [SKIP][138] ([Intel XE#4950]) -> [SKIP][139] ([Intel XE#2321])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_cursor_crc@cursor-random-512x512.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-bmg: [SKIP][140] ([Intel XE#4950]) -> [SKIP][141] ([Intel XE#2320]) +3 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-bmg: [SKIP][142] ([Intel XE#2291]) -> [SKIP][143] ([Intel XE#4950]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [SKIP][144] ([Intel XE#4950]) -> [FAIL][145] ([Intel XE#4633])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-bmg: [SKIP][146] ([Intel XE#1508]) -> [SKIP][147] ([Intel XE#4947])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [SKIP][148] ([Intel XE#4302]) -> [SKIP][149] ([Intel XE#4950])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-bmg: [SKIP][150] ([Intel XE#4947]) -> [SKIP][151] ([Intel XE#4354])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_dp_link_training@uhbr-mst.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
- shard-bmg: [SKIP][152] ([Intel XE#4945]) -> [SKIP][153] ([Intel XE#4422])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
* igt@kms_feature_discovery@psr1:
- shard-bmg: [SKIP][154] ([Intel XE#4950]) -> [SKIP][155] ([Intel XE#2374])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_feature_discovery@psr1.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_feature_discovery@psr1.html
* igt@kms_feature_discovery@psr2:
- shard-bmg: [SKIP][156] ([Intel XE#2374]) -> [SKIP][157] ([Intel XE#4950])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_feature_discovery@psr2.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-bmg: [SKIP][158] ([Intel XE#2316]) -> [SKIP][159] ([Intel XE#4950])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-bmg: [SKIP][160] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][161] ([Intel XE#4947]) +2 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-bmg: [SKIP][162] ([Intel XE#4947]) -> [SKIP][163] ([Intel XE#2293] / [Intel XE#2380]) +3 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt:
- shard-bmg: [SKIP][164] ([Intel XE#2311]) -> [SKIP][165] ([Intel XE#4947]) +23 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][166] ([Intel XE#2312]) -> [SKIP][167] ([Intel XE#2311]) +4 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][168] ([Intel XE#2311]) -> [SKIP][169] ([Intel XE#2312]) +9 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
- shard-bmg: [SKIP][170] ([Intel XE#4947]) -> [SKIP][171] ([Intel XE#2311]) +20 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][172] ([Intel XE#2312]) -> [SKIP][173] ([Intel XE#5390]) +1 other test skip
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][174] ([Intel XE#5390]) -> [SKIP][175] ([Intel XE#2312]) +2 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][176] ([Intel XE#5390]) -> [SKIP][177] ([Intel XE#4947]) +16 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][178] ([Intel XE#4947]) -> [SKIP][179] ([Intel XE#5390]) +7 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
- shard-bmg: [SKIP][180] ([Intel XE#2313]) -> [SKIP][181] ([Intel XE#4947]) +28 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][182] ([Intel XE#2312]) -> [SKIP][183] ([Intel XE#4947]) +8 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][184] ([Intel XE#2312]) -> [SKIP][185] ([Intel XE#2313]) +5 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][186] ([Intel XE#2313]) -> [SKIP][187] ([Intel XE#2312]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][188] ([Intel XE#4947]) -> [SKIP][189] ([Intel XE#2313]) +20 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [SKIP][190] ([Intel XE#1503]) -> [SKIP][191] ([Intel XE#4950]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_hdr@static-toggle.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_hdr@static-toggle.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-bmg: [SKIP][192] ([Intel XE#4950]) -> [SKIP][193] ([Intel XE#2486])
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_panel_fitting@atomic-fastset.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-bmg: [SKIP][194] ([Intel XE#4947]) -> [SKIP][195] ([Intel XE#4329])
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: [SKIP][196] ([Intel XE#2393]) -> [SKIP][197] ([Intel XE#4950])
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@kms_plane_lowres@tiling-yf.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75:
- shard-bmg: [SKIP][198] ([Intel XE#2763]) -> [SKIP][199] ([Intel XE#4950])
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
- shard-bmg: [SKIP][200] ([Intel XE#4950]) -> [SKIP][201] ([Intel XE#2763])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
* igt@kms_pm_backlight@basic-brightness:
- shard-bmg: [SKIP][202] ([Intel XE#4947]) -> [SKIP][203] ([Intel XE#870]) +1 other test skip
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_pm_backlight@basic-brightness.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc5-psr:
- shard-bmg: [SKIP][204] ([Intel XE#2392]) -> [SKIP][205] ([Intel XE#4947])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@kms_pm_dc@dc5-psr.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-bmg: [SKIP][206] ([Intel XE#4962]) -> [SKIP][207] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_pm_rpm@modeset-lpsp.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
- shard-bmg: [SKIP][208] ([Intel XE#4947]) -> [SKIP][209] ([Intel XE#1489]) +5 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: [SKIP][210] ([Intel XE#1489]) -> [SKIP][211] ([Intel XE#4947]) +6 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-bmg: [SKIP][212] ([Intel XE#4947]) -> [SKIP][213] ([Intel XE#2387])
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_psr2_su@page_flip-xrgb8888.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-psr2-cursor-plane-move:
- shard-bmg: [SKIP][214] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][215] ([Intel XE#4947]) +15 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_psr@fbc-psr2-cursor-plane-move.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_psr@fbc-psr2-cursor-plane-move.html
* igt@kms_psr@pr-suspend:
- shard-bmg: [SKIP][216] ([Intel XE#4947]) -> [SKIP][217] ([Intel XE#2234] / [Intel XE#2850]) +9 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_psr@pr-suspend.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_psr@pr-suspend.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: [SKIP][218] ([Intel XE#2414]) -> [SKIP][219] ([Intel XE#4947])
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-bmg: [SKIP][220] ([Intel XE#2330]) -> [SKIP][221] ([Intel XE#4950])
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-bmg: [SKIP][222] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][223] ([Intel XE#4950])
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_rotation_crc@sprite-rotation-270.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-bmg: [SKIP][224] ([Intel XE#2413]) -> [SKIP][225] ([Intel XE#4950])
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_scaling_modes@scaling-mode-center.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-bmg: [SKIP][226] ([Intel XE#4950]) -> [SKIP][227] ([Intel XE#2413])
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][228] ([Intel XE#1500]) -> [SKIP][229] ([Intel XE#362])
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-bmg: [SKIP][230] ([Intel XE#1499]) -> [SKIP][231] ([Intel XE#4950]) +1 other test skip
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@kms_vrr@seamless-rr-switch-drrs.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-bmg: [SKIP][232] ([Intel XE#4950]) -> [SKIP][233] ([Intel XE#1499])
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-virtual.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@xe_eudebug@discovery-empty:
- shard-bmg: [SKIP][234] ([Intel XE#4945]) -> [SKIP][235] ([Intel XE#4837]) +8 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_eudebug@discovery-empty.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@xe_eudebug@discovery-empty.html
* igt@xe_eudebug_online@set-breakpoint-sigint-debugger:
- shard-bmg: [SKIP][236] ([Intel XE#4837]) -> [SKIP][237] ([Intel XE#4945]) +10 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
- shard-bmg: [SKIP][238] ([Intel XE#2322]) -> [SKIP][239] ([Intel XE#4945]) +7 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
- shard-bmg: [SKIP][240] ([Intel XE#4945]) -> [SKIP][241] ([Intel XE#2322]) +5 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html
* igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset:
- shard-bmg: [SKIP][242] ([Intel XE#4943]) -> [SKIP][243] ([Intel XE#4945]) +21 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_exec_system_allocator@many-execqueues-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: [SKIP][244] ([Intel XE#4945]) -> [SKIP][245] ([Intel XE#4943]) +16 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-bmg: [ABORT][246] ([Intel XE#5530]) -> [SKIP][247] ([Intel XE#4945])
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
* igt@xe_media_fill@media-fill:
- shard-bmg: [SKIP][248] ([Intel XE#4945]) -> [SKIP][249] ([Intel XE#2459] / [Intel XE#2596])
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_media_fill@media-fill.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@xe_media_fill@media-fill.html
* igt@xe_pat@pat-index-xelpg:
- shard-bmg: [SKIP][250] ([Intel XE#2236]) -> [SKIP][251] ([Intel XE#4945])
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@xe_pat@pat-index-xelpg.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_pat@pat-index-xelpg.html
* igt@xe_pm@d3cold-mmap-system:
- shard-bmg: [SKIP][252] ([Intel XE#4945]) -> [SKIP][253] ([Intel XE#2284])
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_pm@d3cold-mmap-system.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-3/igt@xe_pm@d3cold-mmap-system.html
* igt@xe_pm@d3cold-mmap-vram:
- shard-bmg: [SKIP][254] ([Intel XE#2284]) -> [SKIP][255] ([Intel XE#4945])
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-1/igt@xe_pm@d3cold-mmap-vram.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_pm@d3cold-mmap-vram.html
* igt@xe_pm@vram-d3cold-threshold:
- shard-bmg: [SKIP][256] ([Intel XE#579]) -> [SKIP][257] ([Intel XE#4945])
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-6/igt@xe_pm@vram-d3cold-threshold.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_pm@vram-d3cold-threshold.html
* igt@xe_pxp@display-black-pxp-fb:
- shard-bmg: [SKIP][258] ([Intel XE#4733]) -> [SKIP][259] ([Intel XE#4945]) +4 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-2/igt@xe_pxp@display-black-pxp-fb.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-5/igt@xe_pxp@display-black-pxp-fb.html
* igt@xe_query@multigpu-query-uc-fw-version-huc:
- shard-bmg: [SKIP][260] ([Intel XE#4945]) -> [SKIP][261] ([Intel XE#944]) +4 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_query@multigpu-query-uc-fw-version-huc.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@xe_query@multigpu-query-uc-fw-version-huc.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-bmg: [SKIP][262] ([Intel XE#4945]) -> [SKIP][263] ([Intel XE#3342]) +1 other test skip
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_sriov_flr@flr-vf1-clear.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-2/igt@xe_sriov_flr@flr-vf1-clear.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-bmg: [SKIP][264] ([Intel XE#4945]) -> [SKIP][265] ([Intel XE#4351])
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678/shard-bmg-5/igt@xe_sriov_scheduling@equal-throughput.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/shard-bmg-1/igt@xe_sriov_scheduling@equal-throughput.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3768]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3768
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
[Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4672]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4672
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
[Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
[Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
[Intel XE#4962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4962
[Intel XE#4963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4963
[Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
[Intel XE#5166]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5166
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
[Intel XE#5679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5679
[Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
Build changes
-------------
* Linux: xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678 -> xe-pw-152251v1
IGT_8478: 3e7c2bd685397f852853878aef4d9c1e4889a28b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-3486-b6a72d53a8082ee6ef701042e7cb8a93d6a2b678: b6a72d53a8082ee6ef701042e7cb8a93d6a2b678
xe-pw-152251v1: 152251v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152251v1/index.html
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