From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: <stable@vger.kernel.org>, Charlton Lin <charlton.lin@intel.com>,
"Khaled Almahallawy" <khaled.almahallawy@intel.com>
Subject: [PATCH 05/19] drm/i915/icl+/tc: Convert AUX powered WARN to a debug message
Date: Tue, 5 Aug 2025 10:36:46 +0300 [thread overview]
Message-ID: <20250805073700.642107-6-imre.deak@intel.com> (raw)
In-Reply-To: <20250805073700.642107-1-imre.deak@intel.com>
The BIOS can leave the AUX power well enabled on an output, even if this
isn't required (on platforms where the AUX power is only needed for an
AUX access). This was observed at least on PTL. To avoid the WARN which
would be triggered by this during the HW readout, convert the WARN to a
debug message.
Cc: stable@vger.kernel.org # v6.8+
Reported-by: Charlton Lin <charlton.lin@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 14042a64375e1..dec54cb0c8c63 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -1494,11 +1494,11 @@ static void intel_tc_port_reset_mode(struct intel_tc_port *tc,
intel_display_power_flush_work(display);
if (!intel_tc_cold_requires_aux_pw(dig_port)) {
enum intel_display_power_domain aux_domain;
- bool aux_powered;
aux_domain = intel_aux_power_domain(dig_port);
- aux_powered = intel_display_power_is_enabled(display, aux_domain);
- drm_WARN_ON(display->drm, aux_powered);
+ if (intel_display_power_is_enabled(display, aux_domain))
+ drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n",
+ tc->port_name);
}
tc_phy_disconnect(tc);
--
2.49.1
next prev parent reply other threads:[~2025-08-05 7:37 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 7:36 [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Imre Deak
2025-08-05 7:36 ` [PATCH 01/19] drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink Imre Deak
2025-08-07 7:06 ` Kahola, Mika
2025-08-07 10:59 ` Luca Coelho
2025-08-07 11:38 ` Imre Deak
2025-08-07 12:19 ` Jani Nikula
2025-08-07 12:32 ` Imre Deak
2025-08-07 12:50 ` Imre Deak
2025-08-07 13:05 ` Jani Nikula
2025-08-07 13:24 ` Imre Deak
2025-08-07 14:10 ` Luca Coelho
2025-08-05 7:36 ` [PATCH 02/19] drm/i915/icl+/tc: Cache the max lane count value Imre Deak
2025-08-05 9:33 ` [PATCH v2 " Imre Deak
2025-08-07 8:07 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 03/19] drm/i915/lnl+/tc: Fix max lane count HW readout Imre Deak
2025-08-05 9:33 ` [PATCH v2 " Imre Deak
2025-08-07 8:36 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 04/19] drm/i915/lnl+/tc: Use the cached max lane count value Imre Deak
2025-08-07 8:49 ` Kahola, Mika
2025-08-05 7:36 ` Imre Deak [this message]
2025-08-07 12:29 ` [PATCH 05/19] drm/i915/icl+/tc: Convert AUX powered WARN to a debug message Kahola, Mika
2025-08-05 7:36 ` [PATCH 06/19] drm/i915/tc: Use the cached max lane count value Imre Deak
2025-08-06 12:02 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 07/19] drm/i915/tc: Move getting the power domain before reading DFLEX registers Imre Deak
2025-08-06 12:56 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 08/19] drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUS Imre Deak
2025-08-06 13:22 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 09/19] drm/i915/tc: Add an enum for the TypeC pin assignment Imre Deak
2025-08-07 12:39 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using the pin assignment enum Imre Deak
2025-08-07 12:56 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 11/19] drm/i915/tc: Handle pin assignment NONE on all platforms Imre Deak
2025-08-07 12:57 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 12/19] drm/i915/tc: Validate the pin assignment " Imre Deak
2025-08-07 13:08 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 13/19] drm/i915/tc: Unify the way to get " Imre Deak
2025-08-08 6:44 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 14/19] drm/i915/tc: Unify the way to get the max lane count value on MTL+ Imre Deak
2025-08-08 7:32 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 15/19] drm/i915/tc: Handle non-TC encoders when getting the pin assignment Imre Deak
2025-08-08 7:45 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 16/19] drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers Imre Deak
2025-08-08 8:25 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 17/19] dmc/i915/tc: Report pin assignment NONE in TBT-alt mode Imre Deak
2025-08-08 8:26 ` Kahola, Mika
2025-08-05 7:36 ` [PATCH 18/19] drm/i915/tc: Cache the pin assignment value Imre Deak
2025-08-08 8:27 ` Kahola, Mika
2025-08-05 7:37 ` [PATCH 19/19] drm/i915/tc: Debug print the pin assignment and max lane count Imre Deak
2025-08-08 8:28 ` Kahola, Mika
2025-08-05 7:46 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Patchwork
2025-08-05 7:47 ` ✓ CI.KUnit: success " Patchwork
2025-08-05 8:02 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05 8:49 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-08-05 10:08 ` ✓ Xe.CI.Full: success " Patchwork
2025-08-05 11:41 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Patchwork
2025-08-05 11:42 ` ✓ CI.KUnit: success " Patchwork
2025-08-05 11:57 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05 13:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-08-05 15:31 ` ✓ Xe.CI.Full: " Patchwork
2025-08-06 11:44 ` [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Luca Coelho
2025-08-06 11:54 ` Imre Deak
2025-08-06 12:54 ` Luca Coelho
2025-08-06 13:12 ` Imre Deak
2025-08-06 13:16 ` Luca Coelho
[not found] ` <175439829105.213103.3969215907569188087@1538d3639d33>
2025-08-13 12:43 ` ✗ i915.CI.Full: failure for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Imre Deak
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