* [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait
@ 2025-08-12 18:28 fei.yang
2025-08-12 18:28 ` [PATCH 1/1] " fei.yang
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: fei.yang @ 2025-08-12 18:28 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, lucas.demarchi, matthew.brost, Fei Yang
From: Fei Yang <fei.yang@intel.com>
Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write operation with
command execution proceeding normally. Although the write operation is
guaranteed to complete eventually, there is no mechanism to synchronize
command execution with the completion (or even initiation) of these
operations."
The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT consecutively
to implement user fence. However, according to the BSpec, the data write
operation is not guaranteed to be completed when triggering the interrupt,
that would cause the xe_wait_user_fence_ioctl to wait until the full user
specified timeout is reached before checking the fence value again. Great
performance degradation has been observed in IGT xe_exec_fault_mode test
cases due to this unnecessary wait. The worst case is that if user set the
timeout to MAX_INT32, the wait could end up being a hang until some other
random program triggers a user interrupt to wake it up.
A semaphore wait is added right after the data write to avoid the unexpected
wait.
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang (1):
drm/xe: serialize store_data and user_interrupt for ufence wait
drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
2 files changed, 25 insertions(+)
--
2.43.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/1] drm/xe: serialize store_data and user_interrupt for ufence wait
2025-08-12 18:28 [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait fei.yang
@ 2025-08-12 18:28 ` fei.yang
2025-08-12 20:07 ` Matthew Brost
2025-08-13 19:53 ` ✗ CI.checkpatch: warning for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2) Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: fei.yang @ 2025-08-12 18:28 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, lucas.demarchi, matthew.brost, Fei Yang
From: Fei Yang <fei.yang@intel.com>
Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write operation with
command execution proceeding normally. Although the write operation is
guaranteed to complete eventually, there is no mechanism to synchronize
command execution with the completion (or even initiation) of these
operations."
The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT consecutively
to implement user fence. However, according to the BSpec, the data write
operation is not guaranteed to be completed when triggering the interrupt,
that would cause the xe_wait_user_fence_ioctl to wait until the full user
specified timeout is reached before checking the fence value again. Great
performance degradation has been observed in IGT xe_exec_fault_mode test
cases due to this unnecessary wait. The worst case is that if user set the
timeout to MAX_INT32, the wait could end up being a hang until some other
random program triggers a user interrupt to wake it up.
A semaphore wait is added right after the data write to avoid the unexpected
wait.
Signed-off-by: Fei Yang <fei.yang@intel.com>
---
drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
index c47b290e0e9f..1c9e7b35c665 100644
--- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
@@ -34,6 +34,17 @@
#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
#define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
+#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
+#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16)
+#define MI_SEMAPHORE_POLL REG_BIT(15)
+#define MI_SEMAPHORE_COMP_OP GENMASK(14, 12)
+#define MI_SEMAPHORE_SAD_GT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 0)
+#define MI_SEMAPHORE_SAD_GTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 1)
+#define MI_SEMAPHORE_SAD_LT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 2)
+#define MI_SEMAPHORE_SAD_LTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 3)
+#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 4)
+#define MI_SEMAPHORE_SAD_NEQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 5)
+
#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
#define MI_SDI_GGTT REG_BIT(22)
#define MI_SDI_LEN_DW GENMASK(9, 0)
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 5f15360d14bf..189e764e3914 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -169,6 +169,20 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
dw[i++] = upper_32_bits(addr);
dw[i++] = lower_32_bits(value);
dw[i++] = upper_32_bits(value);
+ dw[i++] = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ dw[i++] = lower_32_bits(value);
+ dw[i++] = lower_32_bits(addr);
+ dw[i++] = upper_32_bits(addr);
+ dw[i++] = 0;
+ dw[i++] = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ dw[i++] = upper_32_bits(value);
+ dw[i++] = lower_32_bits(addr + 4);
+ dw[i++] = upper_32_bits(addr);
+ dw[i++] = 0;
return i;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/1] drm/xe: serialize store_data and user_interrupt for ufence wait
2025-08-12 18:28 ` [PATCH 1/1] " fei.yang
@ 2025-08-12 20:07 ` Matthew Brost
2025-08-15 21:03 ` Yang, Fei
0 siblings, 1 reply; 11+ messages in thread
From: Matthew Brost @ 2025-08-12 20:07 UTC (permalink / raw)
To: fei.yang; +Cc: intel-xe, matthew.d.roper, lucas.demarchi
On Tue, Aug 12, 2025 at 11:28:46AM -0700, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
>
> Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write operation with
> command execution proceeding normally. Although the write operation is
> guaranteed to complete eventually, there is no mechanism to synchronize
> command execution with the completion (or even initiation) of these
> operations."
Can we not just use update emit_store_imm_ppgtt_posted to use
MI_FLUSH_IMM + a PPGTT address? I think we can get rid of prior flush
added in 3ad7d18c5dad7?
According to bspec 45725 for MI_FLUSH_IMM:
'Usage note: After this command is completed with a Store DWord enabled,
CPU access to graphics memory willbe coherent (assuming the Render Cache
flush is not inhibited).'
Matt
> The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT consecutively
> to implement user fence. However, according to the BSpec, the data write
> operation is not guaranteed to be completed when triggering the interrupt,
> that would cause the xe_wait_user_fence_ioctl to wait until the full user
> specified timeout is reached before checking the fence value again. Great
> performance degradation has been observed in IGT xe_exec_fault_mode test
> cases due to this unnecessary wait. The worst case is that if user set the
> timeout to MAX_INT32, the wait could end up being a hang until some other
> random program triggers a user interrupt to wake it up.
> A semaphore wait is added right after the data write to avoid the unexpected
> wait.
>
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> ---
> drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
> drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> index c47b290e0e9f..1c9e7b35c665 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> @@ -34,6 +34,17 @@
> #define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
> #define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
>
> +#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
> +#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16)
> +#define MI_SEMAPHORE_POLL REG_BIT(15)
> +#define MI_SEMAPHORE_COMP_OP GENMASK(14, 12)
> +#define MI_SEMAPHORE_SAD_GT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 0)
> +#define MI_SEMAPHORE_SAD_GTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 1)
> +#define MI_SEMAPHORE_SAD_LT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 2)
> +#define MI_SEMAPHORE_SAD_LTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 3)
> +#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 4)
> +#define MI_SEMAPHORE_SAD_NEQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 5)
> +
> #define MI_STORE_DATA_IMM __MI_INSTR(0x20)
> #define MI_SDI_GGTT REG_BIT(22)
> #define MI_SDI_LEN_DW GENMASK(9, 0)
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 5f15360d14bf..189e764e3914 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -169,6 +169,20 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
> dw[i++] = upper_32_bits(addr);
> dw[i++] = lower_32_bits(value);
> dw[i++] = upper_32_bits(value);
> + dw[i++] = MI_SEMAPHORE_WAIT |
> + MI_SEMAPHORE_POLL |
> + MI_SEMAPHORE_SAD_EQ_SDD;
> + dw[i++] = lower_32_bits(value);
> + dw[i++] = lower_32_bits(addr);
> + dw[i++] = upper_32_bits(addr);
> + dw[i++] = 0;
> + dw[i++] = MI_SEMAPHORE_WAIT |
> + MI_SEMAPHORE_POLL |
> + MI_SEMAPHORE_SAD_EQ_SDD;
> + dw[i++] = upper_32_bits(value);
> + dw[i++] = lower_32_bits(addr + 4);
> + dw[i++] = upper_32_bits(addr);
> + dw[i++] = 0;
>
> return i;
> }
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
2025-08-12 18:28 [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait fei.yang
2025-08-12 18:28 ` [PATCH 1/1] " fei.yang
@ 2025-08-13 19:53 ` Patchwork
2025-08-13 19:54 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2025-08-13 19:53 UTC (permalink / raw)
To: fei.yang; +Cc: intel-xe
== Series Details ==
Series: drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
URL : https://patchwork.freedesktop.org/series/152847/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
6f9293a391ff3c575bc021f454be5d0a0c076f57
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 3aca4152a2cce49748c02f641047bab24cff585c
Author: Fei Yang <fei.yang@intel.com>
Date: Tue Aug 12 11:28:46 2025 -0700
drm/xe: serialize store_data and user_interrupt for ufence wait
Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write operation with
command execution proceeding normally. Although the write operation is
guaranteed to complete eventually, there is no mechanism to synchronize
command execution with the completion (or even initiation) of these
operations."
The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT consecutively
to implement user fence. However, according to the BSpec, the data write
operation is not guaranteed to be completed when triggering the interrupt,
that would cause the xe_wait_user_fence_ioctl to wait until the full user
specified timeout is reached before checking the fence value again. Great
performance degradation has been observed in IGT xe_exec_fault_mode test
cases due to this unnecessary wait. The worst case is that if user set the
timeout to MAX_INT32, the wait could end up being a hang until some other
random program triggers a user interrupt to wake it up.
A semaphore wait is added right after the data write to avoid the unexpected
wait.
Signed-off-by: Fei Yang <fei.yang@intel.com>
+ /mt/dim checkpatch b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472 drm-intel
3aca4152a2cc drm/xe: serialize store_data and user_interrupt for ufence wait
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#12:
The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT consecutively
total: 0 errors, 1 warnings, 0 checks, 37 lines checked
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ CI.KUnit: success for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
2025-08-12 18:28 [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait fei.yang
2025-08-12 18:28 ` [PATCH 1/1] " fei.yang
2025-08-13 19:53 ` ✗ CI.checkpatch: warning for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2) Patchwork
@ 2025-08-13 19:54 ` Patchwork
2025-08-13 20:56 ` ✓ Xe.CI.BAT: " Patchwork
2025-08-13 22:02 ` ✗ Xe.CI.Full: failure " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2025-08-13 19:54 UTC (permalink / raw)
To: fei.yang; +Cc: intel-xe
== Series Details ==
Series: drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
URL : https://patchwork.freedesktop.org/series/152847/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:53:17] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:53:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:53:50] Starting KUnit Kernel (1/1)...
[19:53:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:53:51] ================== guc_buf (11 subtests) ===================
[19:53:51] [PASSED] test_smallest
[19:53:51] [PASSED] test_largest
[19:53:51] [PASSED] test_granular
[19:53:51] [PASSED] test_unique
[19:53:51] [PASSED] test_overlap
[19:53:51] [PASSED] test_reusable
[19:53:51] [PASSED] test_too_big
[19:53:51] [PASSED] test_flush
[19:53:51] [PASSED] test_lookup
[19:53:51] [PASSED] test_data
[19:53:51] [PASSED] test_class
[19:53:51] ===================== [PASSED] guc_buf =====================
[19:53:51] =================== guc_dbm (7 subtests) ===================
[19:53:51] [PASSED] test_empty
[19:53:51] [PASSED] test_default
[19:53:51] ======================== test_size ========================
[19:53:51] [PASSED] 4
[19:53:51] [PASSED] 8
[19:53:51] [PASSED] 32
[19:53:51] [PASSED] 256
[19:53:51] ==================== [PASSED] test_size ====================
[19:53:51] ======================= test_reuse ========================
[19:53:51] [PASSED] 4
[19:53:51] [PASSED] 8
[19:53:51] [PASSED] 32
[19:53:51] [PASSED] 256
[19:53:51] =================== [PASSED] test_reuse ====================
[19:53:51] =================== test_range_overlap ====================
[19:53:51] [PASSED] 4
[19:53:51] [PASSED] 8
[19:53:51] [PASSED] 32
[19:53:51] [PASSED] 256
[19:53:51] =============== [PASSED] test_range_overlap ================
[19:53:51] =================== test_range_compact ====================
[19:53:51] [PASSED] 4
[19:53:51] [PASSED] 8
[19:53:51] [PASSED] 32
[19:53:51] [PASSED] 256
[19:53:51] =============== [PASSED] test_range_compact ================
[19:53:51] ==================== test_range_spare =====================
[19:53:51] [PASSED] 4
[19:53:51] [PASSED] 8
[19:53:51] [PASSED] 32
[19:53:51] [PASSED] 256
[19:53:51] ================ [PASSED] test_range_spare =================
[19:53:51] ===================== [PASSED] guc_dbm =====================
[19:53:51] =================== guc_idm (6 subtests) ===================
[19:53:51] [PASSED] bad_init
[19:53:51] [PASSED] no_init
[19:53:51] [PASSED] init_fini
[19:53:51] [PASSED] check_used
[19:53:51] [PASSED] check_quota
[19:53:51] [PASSED] check_all
[19:53:51] ===================== [PASSED] guc_idm =====================
[19:53:51] ================== no_relay (3 subtests) ===================
[19:53:51] [PASSED] xe_drops_guc2pf_if_not_ready
[19:53:51] [PASSED] xe_drops_guc2vf_if_not_ready
[19:53:51] [PASSED] xe_rejects_send_if_not_ready
[19:53:51] ==================== [PASSED] no_relay =====================
[19:53:51] ================== pf_relay (14 subtests) ==================
[19:53:51] [PASSED] pf_rejects_guc2pf_too_short
[19:53:51] [PASSED] pf_rejects_guc2pf_too_long
[19:53:51] [PASSED] pf_rejects_guc2pf_no_payload
[19:53:51] [PASSED] pf_fails_no_payload
[19:53:51] [PASSED] pf_fails_bad_origin
[19:53:51] [PASSED] pf_fails_bad_type
[19:53:51] [PASSED] pf_txn_reports_error
[19:53:51] [PASSED] pf_txn_sends_pf2guc
[19:53:51] [PASSED] pf_sends_pf2guc
[19:53:51] [SKIPPED] pf_loopback_nop
[19:53:51] [SKIPPED] pf_loopback_echo
[19:53:51] [SKIPPED] pf_loopback_fail
[19:53:51] [SKIPPED] pf_loopback_busy
[19:53:51] [SKIPPED] pf_loopback_retry
[19:53:51] ==================== [PASSED] pf_relay =====================
[19:53:51] ================== vf_relay (3 subtests) ===================
[19:53:51] [PASSED] vf_rejects_guc2vf_too_short
[19:53:51] [PASSED] vf_rejects_guc2vf_too_long
[19:53:51] [PASSED] vf_rejects_guc2vf_no_payload
[19:53:51] ==================== [PASSED] vf_relay =====================
[19:53:51] ===================== lmtt (1 subtest) =====================
[19:53:51] ======================== test_ops =========================
[19:53:51] [PASSED] 2-level
[19:53:51] [PASSED] multi-level
[19:53:51] ==================== [PASSED] test_ops =====================
[19:53:51] ====================== [PASSED] lmtt =======================
[19:53:51] ================= pf_service (11 subtests) =================
[19:53:51] [PASSED] pf_negotiate_any
[19:53:51] [PASSED] pf_negotiate_base_match
[19:53:51] [PASSED] pf_negotiate_base_newer
[19:53:51] [PASSED] pf_negotiate_base_next
[19:53:51] [SKIPPED] pf_negotiate_base_older
[19:53:51] [PASSED] pf_negotiate_base_prev
[19:53:51] [PASSED] pf_negotiate_latest_match
[19:53:51] [PASSED] pf_negotiate_latest_newer
[19:53:51] [PASSED] pf_negotiate_latest_next
[19:53:51] [SKIPPED] pf_negotiate_latest_older
[19:53:51] [SKIPPED] pf_negotiate_latest_prev
[19:53:51] =================== [PASSED] pf_service ====================
[19:53:51] =================== xe_mocs (2 subtests) ===================
[19:53:51] ================ xe_live_mocs_kernel_kunit ================
[19:53:51] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:53:51] ================ xe_live_mocs_reset_kunit =================
[19:53:51] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:53:51] ==================== [SKIPPED] xe_mocs =====================
[19:53:51] ================= xe_migrate (2 subtests) ==================
[19:53:51] ================= xe_migrate_sanity_kunit =================
[19:53:51] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:53:51] ================== xe_validate_ccs_kunit ==================
[19:53:51] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:53:51] =================== [SKIPPED] xe_migrate ===================
[19:53:51] ================== xe_dma_buf (1 subtest) ==================
[19:53:51] ==================== xe_dma_buf_kunit =====================
[19:53:51] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:53:51] =================== [SKIPPED] xe_dma_buf ===================
[19:53:51] ================= xe_bo_shrink (1 subtest) =================
[19:53:51] =================== xe_bo_shrink_kunit ====================
[19:53:51] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:53:51] ================== [SKIPPED] xe_bo_shrink ==================
[19:53:51] ==================== xe_bo (2 subtests) ====================
[19:53:51] ================== xe_ccs_migrate_kunit ===================
[19:53:51] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:53:51] ==================== xe_bo_evict_kunit ====================
[19:53:51] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:53:51] ===================== [SKIPPED] xe_bo ======================
[19:53:51] ==================== args (11 subtests) ====================
[19:53:51] [PASSED] count_args_test
[19:53:51] [PASSED] call_args_example
[19:53:51] [PASSED] call_args_test
[19:53:51] [PASSED] drop_first_arg_example
[19:53:51] [PASSED] drop_first_arg_test
[19:53:51] [PASSED] first_arg_example
[19:53:51] [PASSED] first_arg_test
[19:53:51] [PASSED] last_arg_example
[19:53:51] [PASSED] last_arg_test
[19:53:51] [PASSED] pick_arg_example
[19:53:51] [PASSED] sep_comma_example
[19:53:51] ====================== [PASSED] args =======================
[19:53:51] =================== xe_pci (3 subtests) ====================
[19:53:51] ==================== check_graphics_ip ====================
[19:53:51] [PASSED] 12.70 Xe_LPG
[19:53:51] [PASSED] 12.71 Xe_LPG
[19:53:51] [PASSED] 12.74 Xe_LPG+
[19:53:51] [PASSED] 20.01 Xe2_HPG
[19:53:51] [PASSED] 20.02 Xe2_HPG
[19:53:51] [PASSED] 20.04 Xe2_LPG
[19:53:51] [PASSED] 30.00 Xe3_LPG
[19:53:51] [PASSED] 30.01 Xe3_LPG
[19:53:51] [PASSED] 30.03 Xe3_LPG
[19:53:51] ================ [PASSED] check_graphics_ip ================
[19:53:51] ===================== check_media_ip ======================
[19:53:51] [PASSED] 13.00 Xe_LPM+
[19:53:51] [PASSED] 13.01 Xe2_HPM
[19:53:51] [PASSED] 20.00 Xe2_LPM
[19:53:51] [PASSED] 30.00 Xe3_LPM
[19:53:51] [PASSED] 30.02 Xe3_LPM
[19:53:51] ================= [PASSED] check_media_ip ==================
[19:53:51] ================= check_platform_gt_count =================
[19:53:51] [PASSED] 0x9A60 (TIGERLAKE)
[19:53:51] [PASSED] 0x9A68 (TIGERLAKE)
[19:53:51] [PASSED] 0x9A70 (TIGERLAKE)
[19:53:51] [PASSED] 0x9A40 (TIGERLAKE)
[19:53:51] [PASSED] 0x9A49 (TIGERLAKE)
[19:53:51] [PASSED] 0x9A59 (TIGERLAKE)
[19:53:51] [PASSED] 0x9A78 (TIGERLAKE)
[19:53:51] [PASSED] 0x9AC0 (TIGERLAKE)
[19:53:51] [PASSED] 0x9AC9 (TIGERLAKE)
[19:53:51] [PASSED] 0x9AD9 (TIGERLAKE)
[19:53:51] [PASSED] 0x9AF8 (TIGERLAKE)
[19:53:51] [PASSED] 0x4C80 (ROCKETLAKE)
[19:53:51] [PASSED] 0x4C8A (ROCKETLAKE)
[19:53:51] [PASSED] 0x4C8B (ROCKETLAKE)
[19:53:51] [PASSED] 0x4C8C (ROCKETLAKE)
[19:53:51] [PASSED] 0x4C90 (ROCKETLAKE)
[19:53:51] [PASSED] 0x4C9A (ROCKETLAKE)
[19:53:51] [PASSED] 0x4680 (ALDERLAKE_S)
[19:53:51] [PASSED] 0x4682 (ALDERLAKE_S)
[19:53:51] [PASSED] 0x4688 (ALDERLAKE_S)
[19:53:51] [PASSED] 0x468A (ALDERLAKE_S)
[19:53:51] [PASSED] 0x468B (ALDERLAKE_S)
[19:53:51] [PASSED] 0x4690 (ALDERLAKE_S)
[19:53:51] [PASSED] 0x4692 (ALDERLAKE_S)
[19:53:51] [PASSED] 0x4693 (ALDERLAKE_S)
[19:53:51] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46AA (ALDERLAKE_P)
[19:53:51] [PASSED] 0x462A (ALDERLAKE_P)
[19:53:51] [PASSED] 0x4626 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x4628 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46B0 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:53:51] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:53:51] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:53:51] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:53:51] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:53:51] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:53:51] [PASSED] 0xA721 (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA720 (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:53:51] [PASSED] 0xA780 (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA781 (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA782 (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA783 (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA788 (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA789 (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA78A (ALDERLAKE_S)
[19:53:51] [PASSED] 0xA78B (ALDERLAKE_S)
[19:53:51] [PASSED] 0x4905 (DG1)
[19:53:51] [PASSED] 0x4906 (DG1)
[19:53:51] [PASSED] 0x4907 (DG1)
[19:53:51] [PASSED] 0x4908 (DG1)
[19:53:51] [PASSED] 0x4909 (DG1)
[19:53:51] [PASSED] 0x56C0 (DG2)
[19:53:51] [PASSED] 0x56C2 (DG2)
[19:53:51] [PASSED] 0x56C1 (DG2)
[19:53:51] [PASSED] 0x7D51 (METEORLAKE)
[19:53:51] [PASSED] 0x7DD1 (METEORLAKE)
[19:53:51] [PASSED] 0x7D41 (METEORLAKE)
[19:53:51] [PASSED] 0x7D67 (METEORLAKE)
[19:53:51] [PASSED] 0xB640 (METEORLAKE)
[19:53:51] [PASSED] 0x56A0 (DG2)
[19:53:51] [PASSED] 0x56A1 (DG2)
[19:53:51] [PASSED] 0x56A2 (DG2)
[19:53:51] [PASSED] 0x56BE (DG2)
[19:53:51] [PASSED] 0x56BF (DG2)
[19:53:51] [PASSED] 0x5690 (DG2)
[19:53:51] [PASSED] 0x5691 (DG2)
[19:53:51] [PASSED] 0x5692 (DG2)
[19:53:51] [PASSED] 0x56A5 (DG2)
[19:53:51] [PASSED] 0x56A6 (DG2)
[19:53:51] [PASSED] 0x56B0 (DG2)
[19:53:51] [PASSED] 0x56B1 (DG2)
[19:53:51] [PASSED] 0x56BA (DG2)
[19:53:51] [PASSED] 0x56BB (DG2)
[19:53:51] [PASSED] 0x56BC (DG2)
[19:53:51] [PASSED] 0x56BD (DG2)
[19:53:51] [PASSED] 0x5693 (DG2)
[19:53:51] [PASSED] 0x5694 (DG2)
[19:53:51] [PASSED] 0x5695 (DG2)
[19:53:51] [PASSED] 0x56A3 (DG2)
[19:53:51] [PASSED] 0x56A4 (DG2)
[19:53:51] [PASSED] 0x56B2 (DG2)
[19:53:51] [PASSED] 0x56B3 (DG2)
[19:53:51] [PASSED] 0x5696 (DG2)
[19:53:51] [PASSED] 0x5697 (DG2)
[19:53:51] [PASSED] 0xB69 (PVC)
[19:53:51] [PASSED] 0xB6E (PVC)
[19:53:51] [PASSED] 0xBD4 (PVC)
[19:53:51] [PASSED] 0xBD5 (PVC)
[19:53:51] [PASSED] 0xBD6 (PVC)
[19:53:51] [PASSED] 0xBD7 (PVC)
[19:53:51] [PASSED] 0xBD8 (PVC)
[19:53:51] [PASSED] 0xBD9 (PVC)
[19:53:51] [PASSED] 0xBDA (PVC)
[19:53:51] [PASSED] 0xBDB (PVC)
[19:53:51] [PASSED] 0xBE0 (PVC)
[19:53:51] [PASSED] 0xBE1 (PVC)
[19:53:51] [PASSED] 0xBE5 (PVC)
[19:53:51] [PASSED] 0x7D40 (METEORLAKE)
[19:53:51] [PASSED] 0x7D45 (METEORLAKE)
[19:53:51] [PASSED] 0x7D55 (METEORLAKE)
[19:53:51] [PASSED] 0x7D60 (METEORLAKE)
[19:53:51] [PASSED] 0x7DD5 (METEORLAKE)
[19:53:51] [PASSED] 0x6420 (LUNARLAKE)
[19:53:51] [PASSED] 0x64A0 (LUNARLAKE)
[19:53:51] [PASSED] 0x64B0 (LUNARLAKE)
[19:53:51] [PASSED] 0xE202 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE209 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE20B (BATTLEMAGE)
[19:53:51] [PASSED] 0xE20C (BATTLEMAGE)
[19:53:51] [PASSED] 0xE20D (BATTLEMAGE)
[19:53:51] [PASSED] 0xE210 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE211 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE212 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE216 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE220 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE221 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE222 (BATTLEMAGE)
[19:53:51] [PASSED] 0xE223 (BATTLEMAGE)
[19:53:51] [PASSED] 0xB080 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB081 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB082 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB083 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB084 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB085 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB086 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB087 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB08F (PANTHERLAKE)
[19:53:51] [PASSED] 0xB090 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:53:51] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:53:51] [PASSED] 0xFD80 (PANTHERLAKE)
[19:53:51] [PASSED] 0xFD81 (PANTHERLAKE)
[19:53:51] ============= [PASSED] check_platform_gt_count =============
[19:53:51] ===================== [PASSED] xe_pci ======================
[19:53:51] =================== xe_rtp (2 subtests) ====================
[19:53:51] =============== xe_rtp_process_to_sr_tests ================
[19:53:51] [PASSED] coalesce-same-reg
[19:53:51] [PASSED] no-match-no-add
[19:53:51] [PASSED] match-or
[19:53:51] [PASSED] match-or-xfail
[19:53:51] [PASSED] no-match-no-add-multiple-rules
[19:53:51] [PASSED] two-regs-two-entries
[19:53:51] [PASSED] clr-one-set-other
[19:53:51] [PASSED] set-field
[19:53:51] [PASSED] conflict-duplicate
[19:53:51] [PASSED] conflict-not-disjoint
[19:53:51] [PASSED] conflict-reg-type
[19:53:51] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:53:51] ================== xe_rtp_process_tests ===================
[19:53:51] [PASSED] active1
[19:53:51] [PASSED] active2
[19:53:51] [PASSED] active-inactive
[19:53:51] [PASSED] inactive-active
[19:53:51] [PASSED] inactive-1st_or_active-inactive
[19:53:51] [PASSED] inactive-2nd_or_active-inactive
[19:53:51] [PASSED] inactive-last_or_active-inactive
[19:53:51] [PASSED] inactive-no_or_active-inactive
[19:53:51] ============== [PASSED] xe_rtp_process_tests ===============
[19:53:51] ===================== [PASSED] xe_rtp ======================
[19:53:51] ==================== xe_wa (1 subtest) =====================
[19:53:51] ======================== xe_wa_gt =========================
[19:53:51] [PASSED] TIGERLAKE (B0)
[19:53:51] [PASSED] DG1 (A0)
[19:53:51] [PASSED] DG1 (B0)
[19:53:51] [PASSED] ALDERLAKE_S (A0)
[19:53:51] [PASSED] ALDERLAKE_S (B0)
[19:53:51] [PASSED] ALDERLAKE_S (C0)
[19:53:51] [PASSED] ALDERLAKE_S (D0)
[19:53:51] [PASSED] ALDERLAKE_P (A0)
[19:53:51] [PASSED] ALDERLAKE_P (B0)
[19:53:51] [PASSED] ALDERLAKE_P (C0)
[19:53:51] [PASSED] ALDERLAKE_S_RPLS (D0)
[19:53:51] [PASSED] ALDERLAKE_P_RPLU (E0)
[19:53:51] [PASSED] DG2_G10 (C0)
[19:53:51] [PASSED] DG2_G11 (B1)
[19:53:51] [PASSED] DG2_G12 (A1)
[19:53:51] [PASSED] METEORLAKE (g:A0, m:A0)
[19:53:51] [PASSED] METEORLAKE (g:A0, m:A0)
[19:53:51] [PASSED] METEORLAKE (g:A0, m:A0)
[19:53:51] [PASSED] LUNARLAKE (g:A0, m:A0)
[19:53:51] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[19:53:51] [PASSED] BATTLEMAGE (g:A0, m:A1)
[19:53:51] ==================== [PASSED] xe_wa_gt =====================
[19:53:51] ====================== [PASSED] xe_wa ======================
[19:53:51] ============================================================
[19:53:51] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[19:53:51] Elapsed time: 33.314s total, 4.178s configuring, 28.769s building, 0.330s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:53:51] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:53:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:54:16] Starting KUnit Kernel (1/1)...
[19:54:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:54:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:54:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:54:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:54:16] =========== drm_validate_clone_mode (2 subtests) ===========
[19:54:16] ============== drm_test_check_in_clone_mode ===============
[19:54:16] [PASSED] in_clone_mode
[19:54:16] [PASSED] not_in_clone_mode
[19:54:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:54:16] =============== drm_test_check_valid_clones ===============
[19:54:16] [PASSED] not_in_clone_mode
[19:54:16] [PASSED] valid_clone
[19:54:16] [PASSED] invalid_clone
[19:54:16] =========== [PASSED] drm_test_check_valid_clones ===========
[19:54:16] ============= [PASSED] drm_validate_clone_mode =============
[19:54:16] ============= drm_validate_modeset (1 subtest) =============
[19:54:16] [PASSED] drm_test_check_connector_changed_modeset
[19:54:16] ============== [PASSED] drm_validate_modeset ===============
[19:54:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[19:54:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:54:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[19:54:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:54:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[19:54:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:54:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:54:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[19:54:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:54:16] ============== drm_bridge_alloc (2 subtests) ===============
[19:54:16] [PASSED] drm_test_drm_bridge_alloc_basic
[19:54:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:54:16] ================ [PASSED] drm_bridge_alloc =================
[19:54:16] ================== drm_buddy (7 subtests) ==================
[19:54:16] [PASSED] drm_test_buddy_alloc_limit
[19:54:16] [PASSED] drm_test_buddy_alloc_optimistic
[19:54:16] [PASSED] drm_test_buddy_alloc_pessimistic
[19:54:16] [PASSED] drm_test_buddy_alloc_pathological
[19:54:16] [PASSED] drm_test_buddy_alloc_contiguous
[19:54:16] [PASSED] drm_test_buddy_alloc_clear
[19:54:16] [PASSED] drm_test_buddy_alloc_range_bias
[19:54:16] ==================== [PASSED] drm_buddy ====================
[19:54:16] ============= drm_cmdline_parser (40 subtests) =============
[19:54:16] [PASSED] drm_test_cmdline_force_d_only
[19:54:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:54:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:54:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:54:16] [PASSED] drm_test_cmdline_force_e_only
[19:54:16] [PASSED] drm_test_cmdline_res
[19:54:16] [PASSED] drm_test_cmdline_res_vesa
[19:54:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:54:16] [PASSED] drm_test_cmdline_res_rblank
[19:54:16] [PASSED] drm_test_cmdline_res_bpp
[19:54:16] [PASSED] drm_test_cmdline_res_refresh
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:54:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:54:16] [PASSED] drm_test_cmdline_res_margins_force_on
[19:54:16] [PASSED] drm_test_cmdline_res_vesa_margins
[19:54:16] [PASSED] drm_test_cmdline_name
[19:54:16] [PASSED] drm_test_cmdline_name_bpp
[19:54:16] [PASSED] drm_test_cmdline_name_option
[19:54:16] [PASSED] drm_test_cmdline_name_bpp_option
[19:54:16] [PASSED] drm_test_cmdline_rotate_0
[19:54:16] [PASSED] drm_test_cmdline_rotate_90
[19:54:16] [PASSED] drm_test_cmdline_rotate_180
[19:54:16] [PASSED] drm_test_cmdline_rotate_270
[19:54:16] [PASSED] drm_test_cmdline_hmirror
[19:54:16] [PASSED] drm_test_cmdline_vmirror
[19:54:16] [PASSED] drm_test_cmdline_margin_options
[19:54:16] [PASSED] drm_test_cmdline_multiple_options
[19:54:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:54:16] [PASSED] drm_test_cmdline_extra_and_option
[19:54:16] [PASSED] drm_test_cmdline_freestanding_options
[19:54:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:54:16] [PASSED] drm_test_cmdline_panel_orientation
[19:54:16] ================ drm_test_cmdline_invalid =================
[19:54:16] [PASSED] margin_only
[19:54:16] [PASSED] interlace_only
[19:54:16] [PASSED] res_missing_x
[19:54:16] [PASSED] res_missing_y
[19:54:16] [PASSED] res_bad_y
[19:54:16] [PASSED] res_missing_y_bpp
[19:54:16] [PASSED] res_bad_bpp
[19:54:16] [PASSED] res_bad_refresh
[19:54:16] [PASSED] res_bpp_refresh_force_on_off
[19:54:16] [PASSED] res_invalid_mode
[19:54:16] [PASSED] res_bpp_wrong_place_mode
[19:54:16] [PASSED] name_bpp_refresh
[19:54:16] [PASSED] name_refresh
[19:54:16] [PASSED] name_refresh_wrong_mode
[19:54:16] [PASSED] name_refresh_invalid_mode
[19:54:16] [PASSED] rotate_multiple
[19:54:16] [PASSED] rotate_invalid_val
[19:54:16] [PASSED] rotate_truncated
[19:54:16] [PASSED] invalid_option
[19:54:16] [PASSED] invalid_tv_option
[19:54:16] [PASSED] truncated_tv_option
[19:54:16] ============ [PASSED] drm_test_cmdline_invalid =============
[19:54:16] =============== drm_test_cmdline_tv_options ===============
[19:54:16] [PASSED] NTSC
[19:54:16] [PASSED] NTSC_443
[19:54:16] [PASSED] NTSC_J
[19:54:16] [PASSED] PAL
[19:54:16] [PASSED] PAL_M
[19:54:16] [PASSED] PAL_N
[19:54:16] [PASSED] SECAM
[19:54:16] [PASSED] MONO_525
[19:54:16] [PASSED] MONO_625
[19:54:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:54:16] =============== [PASSED] drm_cmdline_parser ================
[19:54:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:54:16] [PASSED] drm_test_connector_hdmi_init_valid
[19:54:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:54:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:54:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:54:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:54:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:54:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:54:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:54:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:54:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:54:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:54:16] [PASSED] supported_formats=0x3 yuv420_allowed=1
[19:54:16] [PASSED] supported_formats=0x3 yuv420_allowed=0
[19:54:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:54:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:54:16] [PASSED] drm_test_connector_hdmi_init_null_product
[19:54:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:54:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:54:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:54:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:54:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:54:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:54:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:54:16] ========= drm_test_connector_hdmi_init_type_valid =========
[19:54:16] [PASSED] HDMI-A
[19:54:16] [PASSED] HDMI-B
[19:54:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:54:16] ======== drm_test_connector_hdmi_init_type_invalid ========
[19:54:16] [PASSED] Unknown
[19:54:16] [PASSED] VGA
[19:54:16] [PASSED] DVI-I
[19:54:16] [PASSED] DVI-D
[19:54:16] [PASSED] DVI-A
[19:54:16] [PASSED] Composite
[19:54:16] [PASSED] SVIDEO
[19:54:16] [PASSED] LVDS
[19:54:16] [PASSED] Component
[19:54:16] [PASSED] DIN
[19:54:16] [PASSED] DP
[19:54:16] [PASSED] TV
[19:54:16] [PASSED] eDP
[19:54:16] [PASSED] Virtual
[19:54:16] [PASSED] DSI
[19:54:16] [PASSED] DPI
[19:54:16] [PASSED] Writeback
[19:54:16] [PASSED] SPI
[19:54:16] [PASSED] USB
[19:54:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:54:16] ============ [PASSED] drmm_connector_hdmi_init =============
[19:54:16] ============= drmm_connector_init (3 subtests) =============
[19:54:16] [PASSED] drm_test_drmm_connector_init
[19:54:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:54:16] ========= drm_test_drmm_connector_init_type_valid =========
[19:54:16] [PASSED] Unknown
[19:54:16] [PASSED] VGA
[19:54:16] [PASSED] DVI-I
[19:54:16] [PASSED] DVI-D
[19:54:16] [PASSED] DVI-A
[19:54:16] [PASSED] Composite
[19:54:16] [PASSED] SVIDEO
[19:54:16] [PASSED] LVDS
[19:54:16] [PASSED] Component
[19:54:16] [PASSED] DIN
[19:54:16] [PASSED] DP
[19:54:16] [PASSED] HDMI-A
[19:54:16] [PASSED] HDMI-B
[19:54:16] [PASSED] TV
[19:54:16] [PASSED] eDP
[19:54:16] [PASSED] Virtual
[19:54:16] [PASSED] DSI
[19:54:16] [PASSED] DPI
[19:54:16] [PASSED] Writeback
[19:54:16] [PASSED] SPI
[19:54:16] [PASSED] USB
[19:54:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:54:16] =============== [PASSED] drmm_connector_init ===============
[19:54:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_init
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:54:16] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[19:54:16] [PASSED] Unknown
[19:54:16] [PASSED] VGA
[19:54:16] [PASSED] DVI-I
[19:54:16] [PASSED] DVI-D
[19:54:16] [PASSED] DVI-A
[19:54:16] [PASSED] Composite
[19:54:16] [PASSED] SVIDEO
[19:54:16] [PASSED] LVDS
[19:54:16] [PASSED] Component
[19:54:16] [PASSED] DIN
[19:54:16] [PASSED] DP
[19:54:16] [PASSED] HDMI-A
[19:54:16] [PASSED] HDMI-B
[19:54:16] [PASSED] TV
[19:54:16] [PASSED] eDP
[19:54:16] [PASSED] Virtual
[19:54:16] [PASSED] DSI
[19:54:16] [PASSED] DPI
[19:54:16] [PASSED] Writeback
[19:54:16] [PASSED] SPI
[19:54:16] [PASSED] USB
[19:54:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:54:16] ======== drm_test_drm_connector_dynamic_init_name =========
[19:54:16] [PASSED] Unknown
[19:54:16] [PASSED] VGA
[19:54:16] [PASSED] DVI-I
[19:54:16] [PASSED] DVI-D
[19:54:16] [PASSED] DVI-A
[19:54:16] [PASSED] Composite
[19:54:16] [PASSED] SVIDEO
[19:54:16] [PASSED] LVDS
[19:54:16] [PASSED] Component
[19:54:16] [PASSED] DIN
[19:54:16] [PASSED] DP
[19:54:16] [PASSED] HDMI-A
[19:54:16] [PASSED] HDMI-B
[19:54:16] [PASSED] TV
[19:54:16] [PASSED] eDP
[19:54:16] [PASSED] Virtual
[19:54:16] [PASSED] DSI
[19:54:16] [PASSED] DPI
[19:54:16] [PASSED] Writeback
[19:54:16] [PASSED] SPI
[19:54:16] [PASSED] USB
[19:54:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:54:16] =========== [PASSED] drm_connector_dynamic_init ============
[19:54:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:54:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:54:16] ======= drm_connector_dynamic_register (7 subtests) ========
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:54:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:54:16] ========= [PASSED] drm_connector_dynamic_register ==========
[19:54:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:54:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:54:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:54:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:54:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:54:16] ========== drm_test_get_tv_mode_from_name_valid ===========
[19:54:16] [PASSED] NTSC
[19:54:16] [PASSED] NTSC-443
[19:54:16] [PASSED] NTSC-J
[19:54:16] [PASSED] PAL
[19:54:16] [PASSED] PAL-M
[19:54:16] [PASSED] PAL-N
[19:54:16] [PASSED] SECAM
[19:54:16] [PASSED] Mono
[19:54:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:54:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:54:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:54:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:54:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:54:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:54:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:54:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:54:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:54:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:54:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[19:54:16] [PASSED] VIC 96
[19:54:16] [PASSED] VIC 97
[19:54:16] [PASSED] VIC 101
[19:54:16] [PASSED] VIC 102
[19:54:16] [PASSED] VIC 106
[19:54:16] [PASSED] VIC 107
[19:54:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:54:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:54:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:54:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:54:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:54:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:54:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:54:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:54:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[19:54:16] [PASSED] Automatic
[19:54:16] [PASSED] Full
[19:54:16] [PASSED] Limited 16:235
[19:54:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:54:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:54:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:54:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:54:16] === drm_test_drm_hdmi_connector_get_output_format_name ====
[19:54:16] [PASSED] RGB
[19:54:16] [PASSED] YUV 4:2:0
[19:54:16] [PASSED] YUV 4:2:2
[19:54:16] [PASSED] YUV 4:4:4
[19:54:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:54:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:54:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:54:16] ============= drm_damage_helper (21 subtests) ==============
[19:54:16] [PASSED] drm_test_damage_iter_no_damage
[19:54:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:54:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:54:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:54:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:54:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:54:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:54:16] [PASSED] drm_test_damage_iter_simple_damage
[19:54:16] [PASSED] drm_test_damage_iter_single_damage
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:54:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:54:16] [PASSED] drm_test_damage_iter_damage
[19:54:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:54:16] [PASSED] drm_test_damage_iter_damage_one_outside
[19:54:16] [PASSED] drm_test_damage_iter_damage_src_moved
[19:54:16] [PASSED] drm_test_damage_iter_damage_not_visible
[19:54:16] ================ [PASSED] drm_damage_helper ================
[19:54:16] ============== drm_dp_mst_helper (3 subtests) ==============
[19:54:16] ============== drm_test_dp_mst_calc_pbn_mode ==============
[19:54:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:54:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:54:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:54:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:54:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:54:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:54:16] ============== drm_test_dp_mst_calc_pbn_div ===============
[19:54:16] [PASSED] Link rate 2000000 lane count 4
[19:54:16] [PASSED] Link rate 2000000 lane count 2
[19:54:16] [PASSED] Link rate 2000000 lane count 1
[19:54:16] [PASSED] Link rate 1350000 lane count 4
[19:54:16] [PASSED] Link rate 1350000 lane count 2
[19:54:16] [PASSED] Link rate 1350000 lane count 1
[19:54:16] [PASSED] Link rate 1000000 lane count 4
[19:54:16] [PASSED] Link rate 1000000 lane count 2
[19:54:16] [PASSED] Link rate 1000000 lane count 1
[19:54:16] [PASSED] Link rate 810000 lane count 4
[19:54:16] [PASSED] Link rate 810000 lane count 2
[19:54:16] [PASSED] Link rate 810000 lane count 1
[19:54:16] [PASSED] Link rate 540000 lane count 4
[19:54:16] [PASSED] Link rate 540000 lane count 2
[19:54:16] [PASSED] Link rate 540000 lane count 1
[19:54:16] [PASSED] Link rate 270000 lane count 4
[19:54:16] [PASSED] Link rate 270000 lane count 2
[19:54:16] [PASSED] Link rate 270000 lane count 1
[19:54:16] [PASSED] Link rate 162000 lane count 4
[19:54:16] [PASSED] Link rate 162000 lane count 2
[19:54:16] [PASSED] Link rate 162000 lane count 1
[19:54:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:54:16] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[19:54:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:54:16] [PASSED] DP_POWER_UP_PHY with port number
[19:54:16] [PASSED] DP_POWER_DOWN_PHY with port number
[19:54:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:54:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:54:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:54:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:54:16] [PASSED] DP_QUERY_PAYLOAD with port number
[19:54:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:54:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:54:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:54:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:54:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:54:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:54:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:54:16] [PASSED] DP_REMOTE_I2C_READ with port number
[19:54:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:54:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:54:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:54:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:54:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:54:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:54:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:54:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:54:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:54:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:54:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:54:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:54:16] ================ [PASSED] drm_dp_mst_helper ================
[19:54:16] ================== drm_exec (7 subtests) ===================
[19:54:16] [PASSED] sanitycheck
[19:54:16] [PASSED] test_lock
[19:54:16] [PASSED] test_lock_unlock
[19:54:16] [PASSED] test_duplicates
[19:54:16] [PASSED] test_prepare
[19:54:16] [PASSED] test_prepare_array
[19:54:16] [PASSED] test_multiple_loops
[19:54:16] ==================== [PASSED] drm_exec =====================
[19:54:16] =========== drm_format_helper_test (17 subtests) ===========
[19:54:16] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:54:16] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:54:16] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:54:16] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:54:16] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:54:16] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:54:16] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:54:16] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:54:16] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:54:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:54:16] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:54:16] ============== drm_test_fb_xrgb8888_to_mono ===============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:54:16] ==================== drm_test_fb_swab =====================
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ================ [PASSED] drm_test_fb_swab =================
[19:54:16] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:54:16] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[19:54:16] [PASSED] single_pixel_source_buffer
[19:54:16] [PASSED] single_pixel_clip_rectangle
[19:54:16] [PASSED] well_known_colors
[19:54:16] [PASSED] destination_pitch
[19:54:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:54:16] ================= drm_test_fb_clip_offset =================
[19:54:16] [PASSED] pass through
[19:54:16] [PASSED] horizontal offset
[19:54:16] [PASSED] vertical offset
[19:54:16] [PASSED] horizontal and vertical offset
[19:54:16] [PASSED] horizontal offset (custom pitch)
[19:54:16] [PASSED] vertical offset (custom pitch)
[19:54:16] [PASSED] horizontal and vertical offset (custom pitch)
[19:54:16] ============= [PASSED] drm_test_fb_clip_offset =============
[19:54:16] =================== drm_test_fb_memcpy ====================
[19:54:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:54:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:54:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:54:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:54:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:54:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:54:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:54:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:54:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:54:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:54:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:54:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:54:16] =============== [PASSED] drm_test_fb_memcpy ================
[19:54:16] ============= [PASSED] drm_format_helper_test ==============
[19:54:16] ================= drm_format (18 subtests) =================
[19:54:16] [PASSED] drm_test_format_block_width_invalid
[19:54:16] [PASSED] drm_test_format_block_width_one_plane
[19:54:16] [PASSED] drm_test_format_block_width_two_plane
[19:54:16] [PASSED] drm_test_format_block_width_three_plane
[19:54:16] [PASSED] drm_test_format_block_width_tiled
[19:54:16] [PASSED] drm_test_format_block_height_invalid
[19:54:16] [PASSED] drm_test_format_block_height_one_plane
[19:54:16] [PASSED] drm_test_format_block_height_two_plane
[19:54:16] [PASSED] drm_test_format_block_height_three_plane
[19:54:16] [PASSED] drm_test_format_block_height_tiled
[19:54:16] [PASSED] drm_test_format_min_pitch_invalid
[19:54:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:54:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:54:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:54:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:54:16] [PASSED] drm_test_format_min_pitch_two_plane
[19:54:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:54:16] [PASSED] drm_test_format_min_pitch_tiled
[19:54:16] =================== [PASSED] drm_format ====================
[19:54:16] ============== drm_framebuffer (10 subtests) ===============
[19:54:16] ========== drm_test_framebuffer_check_src_coords ==========
[19:54:16] [PASSED] Success: source fits into fb
[19:54:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:54:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:54:16] [PASSED] Fail: overflowing fb with source width
[19:54:16] [PASSED] Fail: overflowing fb with source height
[19:54:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:54:16] [PASSED] drm_test_framebuffer_cleanup
[19:54:16] =============== drm_test_framebuffer_create ===============
[19:54:16] [PASSED] ABGR8888 normal sizes
[19:54:16] [PASSED] ABGR8888 max sizes
[19:54:16] [PASSED] ABGR8888 pitch greater than min required
[19:54:16] [PASSED] ABGR8888 pitch less than min required
[19:54:16] [PASSED] ABGR8888 Invalid width
[19:54:16] [PASSED] ABGR8888 Invalid buffer handle
[19:54:16] [PASSED] No pixel format
[19:54:16] [PASSED] ABGR8888 Width 0
[19:54:16] [PASSED] ABGR8888 Height 0
[19:54:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:54:16] [PASSED] ABGR8888 Large buffer offset
[19:54:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:54:16] [PASSED] ABGR8888 Invalid flag
[19:54:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:54:16] [PASSED] ABGR8888 Valid buffer modifier
[19:54:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:54:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] NV12 Normal sizes
[19:54:16] [PASSED] NV12 Max sizes
[19:54:16] [PASSED] NV12 Invalid pitch
[19:54:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:54:16] [PASSED] NV12 different modifier per-plane
[19:54:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:54:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] NV12 Modifier for inexistent plane
[19:54:16] [PASSED] NV12 Handle for inexistent plane
[19:54:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:54:16] [PASSED] YVU420 Normal sizes
[19:54:16] [PASSED] YVU420 Max sizes
[19:54:16] [PASSED] YVU420 Invalid pitch
[19:54:16] [PASSED] YVU420 Different pitches
[19:54:16] [PASSED] YVU420 Different buffer offsets/pitches
[19:54:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:54:16] [PASSED] YVU420 Valid modifier
[19:54:16] [PASSED] YVU420 Different modifiers per plane
[19:54:16] [PASSED] YVU420 Modifier for inexistent plane
[19:54:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:54:16] [PASSED] X0L2 Normal sizes
[19:54:16] [PASSED] X0L2 Max sizes
[19:54:16] [PASSED] X0L2 Invalid pitch
[19:54:16] [PASSED] X0L2 Pitch greater than minimum required
[19:54:16] [PASSED] X0L2 Handle for inexistent plane
[19:54:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:54:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:54:16] [PASSED] X0L2 Valid modifier
[19:54:16] [PASSED] X0L2 Modifier for inexistent plane
[19:54:16] =========== [PASSED] drm_test_framebuffer_create ===========
[19:54:16] [PASSED] drm_test_framebuffer_free
[19:54:16] [PASSED] drm_test_framebuffer_init
[19:54:16] [PASSED] drm_test_framebuffer_init_bad_format
[19:54:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:54:16] [PASSED] drm_test_framebuffer_lookup
[19:54:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:54:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:54:16] ================= [PASSED] drm_framebuffer =================
[19:54:16] ================ drm_gem_shmem (8 subtests) ================
[19:54:16] [PASSED] drm_gem_shmem_test_obj_create
[19:54:16] [PASSED] drm_gem_shmem_test_obj_create_private
[19:54:16] [PASSED] drm_gem_shmem_test_pin_pages
[19:54:16] [PASSED] drm_gem_shmem_test_vmap
[19:54:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:54:16] [PASSED] drm_gem_shmem_test_get_sg_table
[19:54:16] [PASSED] drm_gem_shmem_test_madvise
[19:54:16] [PASSED] drm_gem_shmem_test_purge
[19:54:16] ================== [PASSED] drm_gem_shmem ==================
[19:54:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:54:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[19:54:16] [PASSED] Automatic
[19:54:16] [PASSED] Full
[19:54:16] [PASSED] Limited 16:235
[19:54:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:54:16] [PASSED] drm_test_check_disable_connector
[19:54:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:54:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:54:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:54:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:54:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:54:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:54:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:54:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:54:16] [PASSED] drm_test_check_output_bpc_dvi
[19:54:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:54:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:54:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:54:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:54:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:54:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:54:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:54:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:54:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:54:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:54:16] [PASSED] drm_test_check_broadcast_rgb_value
[19:54:16] [PASSED] drm_test_check_bpc_8_value
[19:54:16] [PASSED] drm_test_check_bpc_10_value
[19:54:16] [PASSED] drm_test_check_bpc_12_value
[19:54:16] [PASSED] drm_test_check_format_value
[19:54:16] [PASSED] drm_test_check_tmds_char_value
[19:54:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:54:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[19:54:16] [PASSED] drm_test_check_mode_valid
[19:54:16] [PASSED] drm_test_check_mode_valid_reject
[19:54:16] [PASSED] drm_test_check_mode_valid_reject_rate
[19:54:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:54:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:54:16] ================= drm_managed (2 subtests) =================
[19:54:16] [PASSED] drm_test_managed_release_action
[19:54:16] [PASSED] drm_test_managed_run_action
[19:54:16] =================== [PASSED] drm_managed ===================
[19:54:16] =================== drm_mm (6 subtests) ====================
[19:54:16] [PASSED] drm_test_mm_init
[19:54:16] [PASSED] drm_test_mm_debug
[19:54:16] [PASSED] drm_test_mm_align32
[19:54:16] [PASSED] drm_test_mm_align64
[19:54:16] [PASSED] drm_test_mm_lowest
[19:54:16] [PASSED] drm_test_mm_highest
[19:54:16] ===================== [PASSED] drm_mm ======================
[19:54:16] ============= drm_modes_analog_tv (5 subtests) =============
[19:54:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:54:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:54:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:54:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:54:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:54:16] =============== [PASSED] drm_modes_analog_tv ===============
[19:54:16] ============== drm_plane_helper (2 subtests) ===============
[19:54:16] =============== drm_test_check_plane_state ================
[19:54:16] [PASSED] clipping_simple
[19:54:16] [PASSED] clipping_rotate_reflect
[19:54:16] [PASSED] positioning_simple
[19:54:16] [PASSED] upscaling
[19:54:16] [PASSED] downscaling
[19:54:16] [PASSED] rounding1
[19:54:16] [PASSED] rounding2
[19:54:16] [PASSED] rounding3
[19:54:16] [PASSED] rounding4
[19:54:16] =========== [PASSED] drm_test_check_plane_state ============
[19:54:16] =========== drm_test_check_invalid_plane_state ============
[19:54:16] [PASSED] positioning_invalid
[19:54:16] [PASSED] upscaling_invalid
[19:54:16] [PASSED] downscaling_invalid
[19:54:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:54:16] ================ [PASSED] drm_plane_helper =================
[19:54:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:54:16] ====== drm_test_connector_helper_tv_get_modes_check =======
[19:54:16] [PASSED] None
[19:54:16] [PASSED] PAL
[19:54:16] [PASSED] NTSC
[19:54:16] [PASSED] Both, NTSC Default
[19:54:16] [PASSED] Both, PAL Default
[19:54:16] [PASSED] Both, NTSC Default, with PAL on command-line
[19:54:16] [PASSED] Both, PAL Default, with NTSC on command-line
[19:54:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:54:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:54:16] ================== drm_rect (9 subtests) ===================
[19:54:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:54:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:54:16] [PASSED] drm_test_rect_clip_scaled_clipped
[19:54:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:54:16] ================= drm_test_rect_intersect =================
[19:54:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:54:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:54:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:54:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:54:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:54:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:54:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:54:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:54:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:54:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:54:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:54:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:54:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:54:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:54:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:54:16] ============= [PASSED] drm_test_rect_intersect =============
[19:54:16] ================ drm_test_rect_calc_hscale ================
[19:54:16] [PASSED] normal use
[19:54:16] [PASSED] out of max range
[19:54:16] [PASSED] out of min range
[19:54:16] [PASSED] zero dst
[19:54:16] [PASSED] negative src
[19:54:16] [PASSED] negative dst
[19:54:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:54:16] ================ drm_test_rect_calc_vscale ================
[19:54:16] [PASSED] normal use
[19:54:16] [PASSED] out of max range
[19:54:16] [PASSED] out of min range
[19:54:16] [PASSED] zero dst
[19:54:16] [PASSED] negative src
[19:54:16] [PASSED] negative dst
[19:54:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:54:16] ================== drm_test_rect_rotate ===================
[19:54:16] [PASSED] reflect-x
[19:54:16] [PASSED] reflect-y
[19:54:16] [PASSED] rotate-0
[19:54:16] [PASSED] rotate-90
[19:54:16] [PASSED] rotate-180
[19:54:16] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[19:54:16] ============== [PASSED] drm_test_rect_rotate ===============
[19:54:16] ================ drm_test_rect_rotate_inv =================
[19:54:16] [PASSED] reflect-x
[19:54:16] [PASSED] reflect-y
[19:54:16] [PASSED] rotate-0
[19:54:16] [PASSED] rotate-90
[19:54:16] [PASSED] rotate-180
[19:54:16] [PASSED] rotate-270
[19:54:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:54:16] ==================== [PASSED] drm_rect =====================
[19:54:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:54:16] ============ drm_test_sysfb_build_fourcc_list =============
[19:54:16] [PASSED] no native formats
[19:54:16] [PASSED] XRGB8888 as native format
[19:54:16] [PASSED] remove duplicates
[19:54:16] [PASSED] convert alpha formats
[19:54:16] [PASSED] random formats
[19:54:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:54:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:54:16] ============================================================
[19:54:16] Testing complete. Ran 616 tests: passed: 616
[19:54:16] Elapsed time: 24.996s total, 1.702s configuring, 23.126s building, 0.147s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:54:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:54:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:54:26] Starting KUnit Kernel (1/1)...
[19:54:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:54:26] ================= ttm_device (5 subtests) ==================
[19:54:26] [PASSED] ttm_device_init_basic
[19:54:26] [PASSED] ttm_device_init_multiple
[19:54:26] [PASSED] ttm_device_fini_basic
[19:54:26] [PASSED] ttm_device_init_no_vma_man
[19:54:26] ================== ttm_device_init_pools ==================
[19:54:26] [PASSED] No DMA allocations, no DMA32 required
[19:54:26] [PASSED] DMA allocations, DMA32 required
[19:54:26] [PASSED] No DMA allocations, DMA32 required
[19:54:26] [PASSED] DMA allocations, no DMA32 required
[19:54:26] ============== [PASSED] ttm_device_init_pools ==============
[19:54:26] =================== [PASSED] ttm_device ====================
[19:54:26] ================== ttm_pool (8 subtests) ===================
[19:54:26] ================== ttm_pool_alloc_basic ===================
[19:54:26] [PASSED] One page
[19:54:26] [PASSED] More than one page
[19:54:26] [PASSED] Above the allocation limit
[19:54:26] [PASSED] One page, with coherent DMA mappings enabled
[19:54:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:54:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:54:26] ============== ttm_pool_alloc_basic_dma_addr ==============
[19:54:26] [PASSED] One page
[19:54:26] [PASSED] More than one page
[19:54:26] [PASSED] Above the allocation limit
[19:54:26] [PASSED] One page, with coherent DMA mappings enabled
[19:54:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:54:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:54:26] [PASSED] ttm_pool_alloc_order_caching_match
[19:54:26] [PASSED] ttm_pool_alloc_caching_mismatch
[19:54:26] [PASSED] ttm_pool_alloc_order_mismatch
[19:54:26] [PASSED] ttm_pool_free_dma_alloc
[19:54:26] [PASSED] ttm_pool_free_no_dma_alloc
[19:54:26] [PASSED] ttm_pool_fini_basic
[19:54:26] ==================== [PASSED] ttm_pool =====================
[19:54:26] ================ ttm_resource (8 subtests) =================
[19:54:26] ================= ttm_resource_init_basic =================
[19:54:26] [PASSED] Init resource in TTM_PL_SYSTEM
[19:54:26] [PASSED] Init resource in TTM_PL_VRAM
[19:54:26] [PASSED] Init resource in a private placement
[19:54:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:54:26] ============= [PASSED] ttm_resource_init_basic =============
[19:54:26] [PASSED] ttm_resource_init_pinned
[19:54:26] [PASSED] ttm_resource_fini_basic
[19:54:26] [PASSED] ttm_resource_manager_init_basic
[19:54:26] [PASSED] ttm_resource_manager_usage_basic
[19:54:26] [PASSED] ttm_resource_manager_set_used_basic
[19:54:26] [PASSED] ttm_sys_man_alloc_basic
[19:54:26] [PASSED] ttm_sys_man_free_basic
[19:54:26] ================== [PASSED] ttm_resource ===================
[19:54:26] =================== ttm_tt (15 subtests) ===================
[19:54:26] ==================== ttm_tt_init_basic ====================
[19:54:26] [PASSED] Page-aligned size
[19:54:26] [PASSED] Extra pages requested
[19:54:26] ================ [PASSED] ttm_tt_init_basic ================
[19:54:26] [PASSED] ttm_tt_init_misaligned
[19:54:26] [PASSED] ttm_tt_fini_basic
[19:54:26] [PASSED] ttm_tt_fini_sg
[19:54:26] [PASSED] ttm_tt_fini_shmem
[19:54:26] [PASSED] ttm_tt_create_basic
[19:54:26] [PASSED] ttm_tt_create_invalid_bo_type
[19:54:26] [PASSED] ttm_tt_create_ttm_exists
[19:54:26] [PASSED] ttm_tt_create_failed
[19:54:26] [PASSED] ttm_tt_destroy_basic
[19:54:26] [PASSED] ttm_tt_populate_null_ttm
[19:54:26] [PASSED] ttm_tt_populate_populated_ttm
[19:54:26] [PASSED] ttm_tt_unpopulate_basic
[19:54:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:54:26] [PASSED] ttm_tt_swapin_basic
[19:54:26] ===================== [PASSED] ttm_tt ======================
[19:54:26] =================== ttm_bo (14 subtests) ===================
[19:54:26] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[19:54:26] [PASSED] Cannot be interrupted and sleeps
[19:54:26] [PASSED] Cannot be interrupted, locks straight away
[19:54:26] [PASSED] Can be interrupted, sleeps
[19:54:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:54:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:54:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:54:26] [PASSED] ttm_bo_reserve_double_resv
[19:54:26] [PASSED] ttm_bo_reserve_interrupted
[19:54:26] [PASSED] ttm_bo_reserve_deadlock
[19:54:26] [PASSED] ttm_bo_unreserve_basic
[19:54:26] [PASSED] ttm_bo_unreserve_pinned
[19:54:26] [PASSED] ttm_bo_unreserve_bulk
[19:54:26] [PASSED] ttm_bo_put_basic
[19:54:26] [PASSED] ttm_bo_put_shared_resv
[19:54:26] [PASSED] ttm_bo_pin_basic
[19:54:26] [PASSED] ttm_bo_pin_unpin_resource
[19:54:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:54:26] ===================== [PASSED] ttm_bo ======================
[19:54:26] ============== ttm_bo_validate (21 subtests) ===============
[19:54:26] ============== ttm_bo_init_reserved_sys_man ===============
[19:54:26] [PASSED] Buffer object for userspace
[19:54:26] [PASSED] Kernel buffer object
[19:54:26] [PASSED] Shared buffer object
[19:54:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:54:26] ============== ttm_bo_init_reserved_mock_man ==============
[19:54:26] [PASSED] Buffer object for userspace
[19:54:26] [PASSED] Kernel buffer object
[19:54:26] [PASSED] Shared buffer object
[19:54:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:54:26] [PASSED] ttm_bo_init_reserved_resv
[19:54:26] ================== ttm_bo_validate_basic ==================
[19:54:26] [PASSED] Buffer object for userspace
[19:54:26] [PASSED] Kernel buffer object
[19:54:26] [PASSED] Shared buffer object
[19:54:26] ============== [PASSED] ttm_bo_validate_basic ==============
[19:54:26] [PASSED] ttm_bo_validate_invalid_placement
[19:54:26] ============= ttm_bo_validate_same_placement ==============
[19:54:26] [PASSED] System manager
[19:54:26] [PASSED] VRAM manager
[19:54:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:54:26] [PASSED] ttm_bo_validate_failed_alloc
[19:54:26] [PASSED] ttm_bo_validate_pinned
[19:54:26] [PASSED] ttm_bo_validate_busy_placement
[19:54:26] ================ ttm_bo_validate_multihop =================
[19:54:26] [PASSED] Buffer object for userspace
[19:54:26] [PASSED] Kernel buffer object
[19:54:26] [PASSED] Shared buffer object
[19:54:26] ============ [PASSED] ttm_bo_validate_multihop =============
[19:54:26] ========== ttm_bo_validate_no_placement_signaled ==========
[19:54:26] [PASSED] Buffer object in system domain, no page vector
[19:54:26] [PASSED] Buffer object in system domain with an existing page vector
[19:54:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:54:26] ======== ttm_bo_validate_no_placement_not_signaled ========
[19:54:26] [PASSED] Buffer object for userspace
[19:54:26] [PASSED] Kernel buffer object
[19:54:26] [PASSED] Shared buffer object
[19:54:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:54:26] [PASSED] ttm_bo_validate_move_fence_signaled
[19:54:26] ========= ttm_bo_validate_move_fence_not_signaled =========
[19:54:26] [PASSED] Waits for GPU
[19:54:26] [PASSED] Tries to lock straight away
[19:54:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:54:26] [PASSED] ttm_bo_validate_happy_evict
[19:54:26] [PASSED] ttm_bo_validate_all_pinned_evict
[19:54:26] [PASSED] ttm_bo_validate_allowed_only_evict
[19:54:26] [PASSED] ttm_bo_validate_deleted_evict
[19:54:26] [PASSED] ttm_bo_validate_busy_domain_evict
[19:54:26] [PASSED] ttm_bo_validate_evict_gutting
[19:54:26] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[19:54:26] ================= [PASSED] ttm_bo_validate =================
[19:54:26] ============================================================
[19:54:26] Testing complete. Ran 101 tests: passed: 101
[19:54:26] Elapsed time: 9.842s total, 1.667s configuring, 7.908s building, 0.220s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
2025-08-12 18:28 [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait fei.yang
` (2 preceding siblings ...)
2025-08-13 19:54 ` ✓ CI.KUnit: success " Patchwork
@ 2025-08-13 20:56 ` Patchwork
2025-08-13 22:02 ` ✗ Xe.CI.Full: failure " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2025-08-13 20:56 UTC (permalink / raw)
To: fei.yang; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1728 bytes --]
== Series Details ==
Series: drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
URL : https://patchwork.freedesktop.org/series/152847/
State : success
== Summary ==
CI Bug Log - changes from xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472_BAT -> xe-pw-152847v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 9)
------------------------------
Missing (2): bat-adlp-vm bat-ptl-vm
Known issues
------------
Here are the changes found in xe-pw-152847v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#5783]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5783
Build changes
-------------
* Linux: xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472 -> xe-pw-152847v2
IGT_8493: 8493
xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472: b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472
xe-pw-152847v2: 152847v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/index.html
[-- Attachment #2: Type: text/html, Size: 2227 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Xe.CI.Full: failure for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
2025-08-12 18:28 [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait fei.yang
` (3 preceding siblings ...)
2025-08-13 20:56 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-08-13 22:02 ` Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2025-08-13 22:02 UTC (permalink / raw)
To: fei.yang; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 51198 bytes --]
== Series Details ==
Series: drm/xe: serialize store_data and user_interrupt for ufence wait (rev2)
URL : https://patchwork.freedesktop.org/series/152847/
State : failure
== Summary ==
CI Bug Log - changes from xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472_FULL -> xe-pw-152847v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-152847v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-152847v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-152847v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-3:
- shard-bmg: [PASS][1] -> [DMESG-WARN][2] +4 other tests dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-1/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-3.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-b:
- shard-lnl: [PASS][3] -> [DMESG-WARN][4] +19 other tests dmesg-warn
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-b.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-b.html
* igt@xe_compute_preempt@compute-preempt-many-all-ram@engine-drm_xe_engine_class_compute:
- shard-lnl: [PASS][5] -> [TIMEOUT][6] +1 other test timeout
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-3/igt@xe_compute_preempt@compute-preempt-many-all-ram@engine-drm_xe_engine_class_compute.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-2/igt@xe_compute_preempt@compute-preempt-many-all-ram@engine-drm_xe_engine_class_compute.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-prefetch:
- shard-bmg: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-prefetch.html
* igt@xe_exec_system_allocator@process-many-large-mmap-nomemset:
- shard-bmg: [PASS][8] -> [FAIL][9] +96 other tests fail
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-3/igt@xe_exec_system_allocator@process-many-large-mmap-nomemset.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@xe_exec_system_allocator@process-many-large-mmap-nomemset.html
* igt@xe_exec_system_allocator@process-many-stride-new-busy-nomemset:
- shard-lnl: [PASS][10] -> [FAIL][11] +148 other tests fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-4/igt@xe_exec_system_allocator@process-many-stride-new-busy-nomemset.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-4/igt@xe_exec_system_allocator@process-many-stride-new-busy-nomemset.html
* igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
- shard-lnl: [PASS][12] -> [ABORT][13] +3 other tests abort
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-5/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-2/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html
#### Warnings ####
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-lnl: [ABORT][14] ([Intel XE#4757]) -> [ABORT][15]
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@xe_exec_system_allocator@process-many-new-prefetch}:
- shard-lnl: [PASS][16] -> [FAIL][17] +3 other tests fail
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-8/igt@xe_exec_system_allocator@process-many-new-prefetch.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-5/igt@xe_exec_system_allocator@process-many-new-prefetch.html
* {igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared}:
- shard-bmg: [PASS][18] -> [FAIL][19]
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-1/igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-1/igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared.html
Known issues
------------
Here are the changes found in xe-pw-152847v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_atomic_transition@plane-all-transition-nonblocking:
- shard-bmg: [PASS][20] -> [DMESG-WARN][21] ([Intel XE#5667]) +2 other tests dmesg-warn
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-1/igt@kms_atomic_transition@plane-all-transition-nonblocking.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_atomic_transition@plane-all-transition-nonblocking.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2327])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-adlp: [PASS][23] -> [DMESG-FAIL][24] ([Intel XE#4543]) +1 other test dmesg-fail
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#1124]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-adlp: NOTRUN -> [SKIP][26] ([Intel XE#316])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-bmg: [PASS][27] -> [SKIP][28] ([Intel XE#2314] / [Intel XE#2894])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-2/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#2191])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-1-displays-2160x1440p:
- shard-adlp: NOTRUN -> [SKIP][30] ([Intel XE#367]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#367])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-436/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2887])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#787]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-dp-4:
- shard-dg2-set2: [PASS][36] -> [INCOMPLETE][37] ([Intel XE#3862])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-dp-4.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#787]) +83 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][39] -> [INCOMPLETE][40] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [PASS][41] -> [INCOMPLETE][42] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][43] ([Intel XE#2705] / [Intel XE#4212])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][44] ([Intel XE#455] / [Intel XE#787]) +12 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-dp-2.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#4416]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-b-dp-2.html
* igt@kms_chamelium_color@ctm-negative:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2325])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-adlp: NOTRUN -> [SKIP][47] ([Intel XE#373]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm:
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#373]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][49] ([Intel XE#1178])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [FAIL][50] ([Intel XE#1188])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-432/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#308])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-bmg: NOTRUN -> [ABORT][52] ([Intel XE#5826])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-bmg: [PASS][53] -> [SKIP][54] ([Intel XE#2291]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][55] -> [FAIL][56] ([Intel XE#5299])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#455]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-436/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-adlp: NOTRUN -> [ABORT][58] ([Intel XE#4847])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: [PASS][59] -> [SKIP][60] ([Intel XE#2373])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-3/igt@kms_feature_discovery@display-2x.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#310])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-bmg: [PASS][62] -> [SKIP][63] ([Intel XE#2316]) +5 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-7/igt@kms_flip@2x-plain-flip.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible:
- shard-bmg: [PASS][64] -> [DMESG-WARN][65] ([Intel XE#5208])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-3/igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-4/igt@kms_flip@flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@flip-vs-dpms-on-nop@b-hdmi-a1:
- shard-adlp: [PASS][66] -> [DMESG-WARN][67] ([Intel XE#4543]) +1 other test dmesg-warn
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-1/igt@kms_flip@flip-vs-dpms-on-nop@b-hdmi-a1.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-9/igt@kms_flip@flip-vs-dpms-on-nop@b-hdmi-a1.html
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-lnl: [PASS][68] -> [DMESG-WARN][69] ([Intel XE#5208])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-4/igt@kms_flip@flip-vs-rmfb-interruptible.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-4/igt@kms_flip@flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-adlp: [PASS][70] -> [DMESG-WARN][71] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#2293] / [Intel XE#2380])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#2293])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move:
- shard-adlp: NOTRUN -> [SKIP][74] ([Intel XE#651])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-adlp: NOTRUN -> [SKIP][75] ([Intel XE#656]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#651]) +8 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][77] ([Intel XE#2313]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#653]) +5 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [PASS][79] -> [SKIP][80] ([Intel XE#1503])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-3/igt@kms_hdr@static-toggle.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_hdr@static-toggle.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg2-set2: NOTRUN -> [SKIP][81] ([Intel XE#870])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][83] ([Intel XE#1489] / [Intel XE#5899]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
- shard-adlp: NOTRUN -> [SKIP][84] ([Intel XE#1489] / [Intel XE#5899])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-pr-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#2850] / [Intel XE#5899] / [Intel XE#929]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-psr-cursor-render:
- shard-adlp: NOTRUN -> [SKIP][86] ([Intel XE#2850] / [Intel XE#5899] / [Intel XE#929])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_psr@fbc-psr-cursor-render.html
* igt@kms_psr@pr-cursor-plane-onoff:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2234] / [Intel XE#2850] / [Intel XE#5899])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@kms_psr@pr-cursor-plane-onoff.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [PASS][88] -> [SKIP][89] ([Intel XE#1435])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-3/igt@kms_setmode@clone-exclusive-crtc.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html
* igt@xe_copy_basic@mem-set-linear-0x3fff:
- shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#1126])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0x3fff.html
* igt@xe_eudebug@basic-vm-access-parameters-faultable:
- shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#4837]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_eudebug@basic-vm-access-parameters-faultable.html
* igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#4837])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram.html
* igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
- shard-adlp: NOTRUN -> [SKIP][93] ([Intel XE#5563] / [Intel XE#688])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
- shard-dg2-set2: [PASS][94] -> [SKIP][95] ([Intel XE#1392]) +5 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
* igt@xe_exec_basic@once-bindexecqueue-userptr-rebind:
- shard-adlp: [PASS][96] -> [DMESG-WARN][97] ([Intel XE#3868])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-9/igt@xe_exec_basic@once-bindexecqueue-userptr-rebind.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_exec_basic@once-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@once-bindexecqueue:
- shard-adlp: NOTRUN -> [SKIP][98] ([Intel XE#288] / [Intel XE#5561]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_exec_fault_mode@once-bindexecqueue.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#288]) +5 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-invalidate-race-imm.html
* igt@xe_exec_system_allocator@many-large-mmap-shared-remap:
- shard-lnl: [PASS][100] -> [DMESG-FAIL][101] ([Intel XE#5213]) +46 other tests dmesg-fail
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-1/igt@xe_exec_system_allocator@many-large-mmap-shared-remap.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-2/igt@xe_exec_system_allocator@many-large-mmap-shared-remap.html
* igt@xe_exec_system_allocator@once-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#4943]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@xe_exec_system_allocator@once-mmap-free-huge.html
* igt@xe_exec_system_allocator@once-mmap-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#4915]) +53 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_exec_system_allocator@once-mmap-nomemset.html
* igt@xe_exec_system_allocator@threads-many-execqueues-free-nomemset:
- shard-bmg: NOTRUN -> [DMESG-FAIL][104] ([Intel XE#5213]) +1 other test dmesg-fail
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-execqueues-free-nomemset.html
* igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-nomemset:
- shard-adlp: NOTRUN -> [SKIP][105] ([Intel XE#4915]) +18 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-free-nomemset:
- shard-bmg: [PASS][106] -> [DMESG-FAIL][107] ([Intel XE#5213]) +24 other tests dmesg-fail
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-free-nomemset.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-free-nomemset.html
* igt@xe_exec_threads@threads-mixed-shared-vm-basic:
- shard-lnl: [PASS][108] -> [DMESG-FAIL][109] ([Intel XE#3876] / [Intel XE#5213])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-7/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-7/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html
* igt@xe_exec_threads@threads-shared-vm-userptr-invalidate-race:
- shard-lnl: [PASS][110] -> [DMESG-WARN][111] ([Intel XE#5213]) +12 other tests dmesg-warn
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-3/igt@xe_exec_threads@threads-shared-vm-userptr-invalidate-race.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-2/igt@xe_exec_threads@threads-shared-vm-userptr-invalidate-race.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early:
- shard-adlp: [PASS][112] -> [DMESG-WARN][113] ([Intel XE#5732])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-2/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html
* igt@xe_oa@buffer-size:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#5103])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_oa@buffer-size.html
* igt@xe_oa@missing-sample-flags:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#3573])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_oa@missing-sample-flags.html
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][116] ([Intel XE#1173]) +1 other test fail
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-436/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-bmg: [PASS][117] -> [DMESG-WARN][118] ([Intel XE#5213] / [Intel XE#569])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-3/igt@xe_pm@s3-vm-bind-unbind-all.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_pxp@pxp-stale-bo-bind-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#4733])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-5/igt@xe_pxp@pxp-stale-bo-bind-post-suspend.html
* igt@xe_query@multigpu-query-hwconfig:
- shard-dg2-set2: NOTRUN -> [SKIP][120] ([Intel XE#944])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_query@multigpu-query-hwconfig.html
* igt@xe_spin_batch@spin-mem-copy:
- shard-dg2-set2: NOTRUN -> [SKIP][121] ([Intel XE#4821])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_spin_batch@spin-mem-copy.html
* igt@xe_vm@large-userptr-split-misaligned-binds-67108864:
- shard-bmg: [PASS][122] -> [DMESG-WARN][123] ([Intel XE#5213]) +2 other tests dmesg-warn
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-2/igt@xe_vm@large-userptr-split-misaligned-binds-67108864.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-3/igt@xe_vm@large-userptr-split-misaligned-binds-67108864.html
* igt@xe_wedged@wedged-at-any-timeout:
- shard-lnl: [PASS][124] -> [DMESG-WARN][125] ([Intel XE#3119] / [Intel XE#5213])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-7/igt@xe_wedged@wedged-at-any-timeout.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-7/igt@xe_wedged@wedged-at-any-timeout.html
#### Possible fixes ####
* igt@kms_concurrent@multi-plane-atomic-lowres@pipe-a-hdmi-a-6:
- shard-dg2-set2: [ABORT][126] ([Intel XE#5826] / [Intel XE#5898]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-436/igt@kms_concurrent@multi-plane-atomic-lowres@pipe-a-hdmi-a-6.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-436/igt@kms_concurrent@multi-plane-atomic-lowres@pipe-a-hdmi-a-6.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-bmg: [SKIP][128] ([Intel XE#2291]) -> [PASS][129] +1 other test pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-6/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-dg2-set2: [ABORT][130] ([Intel XE#5826]) -> [PASS][131] +1 other test pass
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-435/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-bmg: [DMESG-WARN][132] ([Intel XE#5354]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-6/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [FAIL][134] ([Intel XE#301]) -> [PASS][135] +1 other test pass
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-rmfb:
- shard-adlp: [DMESG-WARN][136] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-4/igt@kms_flip@flip-vs-rmfb.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-6/igt@kms_flip@flip-vs-rmfb.html
* igt@kms_flip@flip-vs-rmfb@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][138] ([Intel XE#4543]) -> [PASS][139] +3 other tests pass
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-4/igt@kms_flip@flip-vs-rmfb@b-hdmi-a1.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-6/igt@kms_flip@flip-vs-rmfb@b-hdmi-a1.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][140] ([Intel XE#1503]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
* igt@kms_vblank@ts-continuation-dpms-suspend:
- shard-adlp: [DMESG-WARN][142] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][143] +3 other tests pass
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-6/igt@kms_vblank@ts-continuation-dpms-suspend.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-2/igt@kms_vblank@ts-continuation-dpms-suspend.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][144] ([Intel XE#4459]) -> [PASS][145] +1 other test pass
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
- shard-dg2-set2: [SKIP][146] ([Intel XE#1392]) -> [PASS][147] +3 other tests pass
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-434/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
* igt@xe_exec_compute_mode@many-execqueues-bindexecqueue-rebind:
- shard-bmg: [FAIL][148] -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-1/igt@xe_exec_compute_mode@many-execqueues-bindexecqueue-rebind.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@xe_exec_compute_mode@many-execqueues-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-imm:
- shard-lnl: [FAIL][150] -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-lnl-1/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-imm.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-lnl-2/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-imm.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-adlp: [DMESG-WARN][152] ([Intel XE#3876]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-2/igt@xe_exec_reset@parallel-gt-reset.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_threads@threads-hang-fd-userptr-rebind:
- shard-dg2-set2: [DMESG-WARN][154] ([Intel XE#3876]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-434/igt@xe_exec_threads@threads-hang-fd-userptr-rebind.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-432/igt@xe_exec_threads@threads-hang-fd-userptr-rebind.html
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- shard-adlp: [DMESG-WARN][156] ([Intel XE#2953] / [Intel XE#4173]) -> [ABORT][157] ([Intel XE#5826])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-4/igt@core_hotunplug@unbind-rebind.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-6/igt@core_hotunplug@unbind-rebind.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][158] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [INCOMPLETE][159] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][160] ([Intel XE#2312]) -> [SKIP][161] ([Intel XE#2311])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render:
- shard-bmg: [SKIP][162] ([Intel XE#2312]) -> [SKIP][163] ([Intel XE#5390])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][164] ([Intel XE#5390]) -> [SKIP][165] ([Intel XE#2312]) +4 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][166] ([Intel XE#2311]) -> [SKIP][167] ([Intel XE#2312]) +12 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][168] ([Intel XE#2313]) -> [SKIP][169] ([Intel XE#2312]) +8 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][170] ([Intel XE#2312]) -> [SKIP][171] ([Intel XE#2313]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-adlp: [ABORT][172] ([Intel XE#5545]) -> [SKIP][173] ([Intel XE#5915])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-adlp-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-adlp-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: [FAIL][174] ([Intel XE#1729]) -> [SKIP][175] ([Intel XE#362])
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][176] ([Intel XE#362]) -> [SKIP][177] ([Intel XE#1500])
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3119]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3119
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4757]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4757
[Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4847]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4847
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5103]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5103
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5563]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5563
[Intel XE#5667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5667
[Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
[Intel XE#5732]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5732
[Intel XE#5826]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5826
[Intel XE#5898]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5898
[Intel XE#5899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5899
[Intel XE#5915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5915
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472 -> xe-pw-152847v2
IGT_8493: 8493
xe-3541-b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472: b6d374ca303d7b9f6456bc6db0cfe6e4d30bf472
xe-pw-152847v2: 152847v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152847v2/index.html
[-- Attachment #2: Type: text/html, Size: 58779 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/1] drm/xe: serialize store_data and user_interrupt for ufence wait
2025-08-12 20:07 ` Matthew Brost
@ 2025-08-15 21:03 ` Yang, Fei
2025-08-15 21:08 ` Matthew Brost
0 siblings, 1 reply; 11+ messages in thread
From: Yang, Fei @ 2025-08-15 21:03 UTC (permalink / raw)
To: Brost, Matthew
Cc: intel-xe@lists.freedesktop.org, Roper, Matthew D,
De Marchi, Lucas
> On Tue, Aug 12, 2025 at 11:28:46AM -0700, fei.yang@intel.com wrote:
>> From: Fei Yang <fei.yang@intel.com>
>>
>> Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write operation
>> with command execution proceeding normally. Although the write
>> operation is guaranteed to complete eventually, there is no mechanism
>> to synchronize command execution with the completion (or even
>> initiation) of these operations."
>
> Can we not just use update emit_store_imm_ppgtt_posted to use MI_FLUSH_IMM +
> a PPGTT address? I think we can get rid of prior flush added in 3ad7d18c5dad7?
>
> According to bspec 45725 for MI_FLUSH_IMM:
>
> 'Usage note: After this command is completed with a Store DWord enabled, CPU
> access to graphics memory willbe coherent (assuming the Render Cache flush is
> not inhibited).'
We already have a MI_FLUSH_DW in between the MI_STORE_DATA_IMM and
MI_USER_INTERRUPT (See __emit_job_gen12_simple), but the issue was
still reporduced.
static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32 *dw, int i)
{
dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
flags;
dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
dw[i++] = 0;
dw[i++] = value;
return i;
}
> Matt
>
>> The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT
>> consecutively to implement user fence. However, according to the
>> BSpec, the data write operation is not guaranteed to be completed when
>> triggering the interrupt, that would cause the
>> xe_wait_user_fence_ioctl to wait until the full user specified timeout
>> is reached before checking the fence value again. Great performance
>> degradation has been observed in IGT xe_exec_fault_mode test cases due
>> to this unnecessary wait. The worst case is that if user set the
>> timeout to MAX_INT32, the wait could end up being a hang until some other random program triggers a user interrupt to wake it up.
>> A semaphore wait is added right after the data write to avoid the
>> unexpected wait.
>>
>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>> ---
>> drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
>> drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>> b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>> index c47b290e0e9f..1c9e7b35c665 100644
>> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>> @@ -34,6 +34,17 @@
>> #define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
>> #define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
>>
>> +#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
>> +#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16)
>> +#define MI_SEMAPHORE_POLL REG_BIT(15)
>> +#define MI_SEMAPHORE_COMP_OP GENMASK(14, 12)
>> +#define MI_SEMAPHORE_SAD_GT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 0)
>> +#define MI_SEMAPHORE_SAD_GTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 1)
>> +#define MI_SEMAPHORE_SAD_LT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 2)
>> +#define MI_SEMAPHORE_SAD_LTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 3)
>> +#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 4)
>> +#define MI_SEMAPHORE_SAD_NEQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 5)
>> +
>> #define MI_STORE_DATA_IMM __MI_INSTR(0x20)
>> #define MI_SDI_GGTT REG_BIT(22)
>> #define MI_SDI_LEN_DW GENMASK(9, 0)
>> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
>> b/drivers/gpu/drm/xe/xe_ring_ops.c
>> index 5f15360d14bf..189e764e3914 100644
>> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
>> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>> @@ -169,6 +169,20 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
>> dw[i++] = upper_32_bits(addr);
>> dw[i++] = lower_32_bits(value);
>> dw[i++] = upper_32_bits(value);
>> + dw[i++] = MI_SEMAPHORE_WAIT |
>> + MI_SEMAPHORE_POLL |
>> + MI_SEMAPHORE_SAD_EQ_SDD;
>> + dw[i++] = lower_32_bits(value);
>> + dw[i++] = lower_32_bits(addr);
>> + dw[i++] = upper_32_bits(addr);
>> + dw[i++] = 0;
>> + dw[i++] = MI_SEMAPHORE_WAIT |
>> + MI_SEMAPHORE_POLL |
>> + MI_SEMAPHORE_SAD_EQ_SDD;
>> + dw[i++] = upper_32_bits(value);
>> + dw[i++] = lower_32_bits(addr + 4);
>> + dw[i++] = upper_32_bits(addr);
>> + dw[i++] = 0;
>>
>> return i;
>> }
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/1] drm/xe: serialize store_data and user_interrupt for ufence wait
2025-08-15 21:03 ` Yang, Fei
@ 2025-08-15 21:08 ` Matthew Brost
2025-08-15 21:28 ` Yang, Fei
0 siblings, 1 reply; 11+ messages in thread
From: Matthew Brost @ 2025-08-15 21:08 UTC (permalink / raw)
To: Yang, Fei
Cc: intel-xe@lists.freedesktop.org, Roper, Matthew D,
De Marchi, Lucas
On Fri, Aug 15, 2025 at 03:03:33PM -0600, Yang, Fei wrote:
> > On Tue, Aug 12, 2025 at 11:28:46AM -0700, fei.yang@intel.com wrote:
> >> From: Fei Yang <fei.yang@intel.com>
> >>
> >> Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write operation
> >> with command execution proceeding normally. Although the write
> >> operation is guaranteed to complete eventually, there is no mechanism
> >> to synchronize command execution with the completion (or even
> >> initiation) of these operations."
> >
> > Can we not just use update emit_store_imm_ppgtt_posted to use MI_FLUSH_IMM +
> > a PPGTT address? I think we can get rid of prior flush added in 3ad7d18c5dad7?
> >
> > According to bspec 45725 for MI_FLUSH_IMM:
> >
> > 'Usage note: After this command is completed with a Store DWord enabled, CPU
> > access to graphics memory willbe coherent (assuming the Render Cache flush is
> > not inhibited).'
>
> We already have a MI_FLUSH_DW in between the MI_STORE_DATA_IMM and
> MI_USER_INTERRUPT (See __emit_job_gen12_simple), but the issue was
> still reporduced.
>
That is not what I'm suggesting. I'm suggesting convert
emit_store_imm_ppgtt_posted to use a MI_FLUSH_DW intruction rather than
MI_STORE_DATA_IMM.
Matt
> static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32 *dw, int i)
> {
> dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
> flags;
> dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
> dw[i++] = 0;
> dw[i++] = value;
>
> return i;
> }
>
> > Matt
> >
> >> The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT
> >> consecutively to implement user fence. However, according to the
> >> BSpec, the data write operation is not guaranteed to be completed when
> >> triggering the interrupt, that would cause the
> >> xe_wait_user_fence_ioctl to wait until the full user specified timeout
> >> is reached before checking the fence value again. Great performance
> >> degradation has been observed in IGT xe_exec_fault_mode test cases due
> >> to this unnecessary wait. The worst case is that if user set the
> >> timeout to MAX_INT32, the wait could end up being a hang until some other random program triggers a user interrupt to wake it up.
> >> A semaphore wait is added right after the data write to avoid the
> >> unexpected wait.
> >>
> >> Signed-off-by: Fei Yang <fei.yang@intel.com>
> >> ---
> >> drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
> >> drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
> >> 2 files changed, 25 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> index c47b290e0e9f..1c9e7b35c665 100644
> >> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >> @@ -34,6 +34,17 @@
> >> #define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
> >> #define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
> >>
> >> +#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
> >> +#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16)
> >> +#define MI_SEMAPHORE_POLL REG_BIT(15)
> >> +#define MI_SEMAPHORE_COMP_OP GENMASK(14, 12)
> >> +#define MI_SEMAPHORE_SAD_GT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 0)
> >> +#define MI_SEMAPHORE_SAD_GTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 1)
> >> +#define MI_SEMAPHORE_SAD_LT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 2)
> >> +#define MI_SEMAPHORE_SAD_LTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 3)
> >> +#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 4)
> >> +#define MI_SEMAPHORE_SAD_NEQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 5)
> >> +
> >> #define MI_STORE_DATA_IMM __MI_INSTR(0x20)
> >> #define MI_SDI_GGTT REG_BIT(22)
> >> #define MI_SDI_LEN_DW GENMASK(9, 0)
> >> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
> >> b/drivers/gpu/drm/xe/xe_ring_ops.c
> >> index 5f15360d14bf..189e764e3914 100644
> >> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> >> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> >> @@ -169,6 +169,20 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
> >> dw[i++] = upper_32_bits(addr);
> >> dw[i++] = lower_32_bits(value);
> >> dw[i++] = upper_32_bits(value);
> >> + dw[i++] = MI_SEMAPHORE_WAIT |
> >> + MI_SEMAPHORE_POLL |
> >> + MI_SEMAPHORE_SAD_EQ_SDD;
> >> + dw[i++] = lower_32_bits(value);
> >> + dw[i++] = lower_32_bits(addr);
> >> + dw[i++] = upper_32_bits(addr);
> >> + dw[i++] = 0;
> >> + dw[i++] = MI_SEMAPHORE_WAIT |
> >> + MI_SEMAPHORE_POLL |
> >> + MI_SEMAPHORE_SAD_EQ_SDD;
> >> + dw[i++] = upper_32_bits(value);
> >> + dw[i++] = lower_32_bits(addr + 4);
> >> + dw[i++] = upper_32_bits(addr);
> >> + dw[i++] = 0;
> >>
> >> return i;
> >> }
> >> --
> >> 2.43.0
> >>
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/1] drm/xe: serialize store_data and user_interrupt for ufence wait
2025-08-15 21:08 ` Matthew Brost
@ 2025-08-15 21:28 ` Yang, Fei
2025-09-03 15:09 ` Matt Roper
0 siblings, 1 reply; 11+ messages in thread
From: Yang, Fei @ 2025-08-15 21:28 UTC (permalink / raw)
To: Brost, Matthew
Cc: intel-xe@lists.freedesktop.org, Roper, Matthew D,
De Marchi, Lucas
> On Fri, Aug 15, 2025 at 03:03:33PM -0600, Yang, Fei wrote:
>>> On Tue, Aug 12, 2025 at 11:28:46AM -0700, fei.yang@intel.com wrote:
>>>> From: Fei Yang <fei.yang@intel.com>
>>>>
>>>> Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write
>>>> operation with command execution proceeding normally. Although the
>>>> write operation is guaranteed to complete eventually, there is no
>>>> mechanism to synchronize command execution with the completion (or
>>>> even
>>>> initiation) of these operations."
>>>
>>> Can we not just use update emit_store_imm_ppgtt_posted to use
>>> MI_FLUSH_IMM + a PPGTT address? I think we can get rid of prior flush added in 3ad7d18c5dad7?
>>>
>>> According to bspec 45725 for MI_FLUSH_IMM:
>>>
>>> 'Usage note: After this command is completed with a Store DWord
>>> enabled, CPU access to graphics memory willbe coherent (assuming the
>>> Render Cache flush is not inhibited).'
>>
>> We already have a MI_FLUSH_DW in between the MI_STORE_DATA_IMM and
>> MI_USER_INTERRUPT (See __emit_job_gen12_simple), but the issue was
>> still reporduced.
>>
>
> That is not what I'm suggesting. I'm suggesting convert emit_store_imm_ppgtt_posted
> to use a MI_FLUSH_DW intruction rather than MI_STORE_DATA_IMM.
Oh, sorry I misunderstood. Yes, that looks promising. At least the BSpec
says CPU access would be coherent, but I'm not sure what would happen
in the case where the write is triggering a page fault. Will give it a
shot and send a different patch if it works.
-Fei
> Matt
>
>> static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32
>> *dw, int i) {
>> dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
>> flags;
>> dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
>> dw[i++] = 0;
>> dw[i++] = value;
>>
>> return i;
>> }
>>
>>> Matt
>>>
>>>> The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT
>>>> consecutively to implement user fence. However, according to the
>>>> BSpec, the data write operation is not guaranteed to be completed
>>>> when triggering the interrupt, that would cause the
>>>> xe_wait_user_fence_ioctl to wait until the full user specified
>>>> timeout is reached before checking the fence value again. Great
>>>> performance degradation has been observed in IGT xe_exec_fault_mode
>>>> test cases due to this unnecessary wait. The worst case is that if
>>>> user set the timeout to MAX_INT32, the wait could end up being a hang until some other random program triggers a user interrupt to wake it up.
>>>> A semaphore wait is added right after the data write to avoid the
>>>> unexpected wait.
>>>>
>>>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
>>>> drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
>>>> 2 files changed, 25 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>>>> b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>>>> index c47b290e0e9f..1c9e7b35c665 100644
>>>> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>>>> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>>>> @@ -34,6 +34,17 @@
>>>> #define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
>>>> #define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
>>>>
>>>> +#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
>>>> +#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16)
>>>> +#define MI_SEMAPHORE_POLL REG_BIT(15)
>>>> +#define MI_SEMAPHORE_COMP_OP GENMASK(14, 12)
>>>> +#define MI_SEMAPHORE_SAD_GT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 0)
>>>> +#define MI_SEMAPHORE_SAD_GTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 1)
>>>> +#define MI_SEMAPHORE_SAD_LT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 2)
>>>> +#define MI_SEMAPHORE_SAD_LTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 3)
>>>> +#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 4)
>>>> +#define MI_SEMAPHORE_SAD_NEQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 5)
>>>> +
>>>> #define MI_STORE_DATA_IMM __MI_INSTR(0x20)
>>>> #define MI_SDI_GGTT REG_BIT(22)
>>>> #define MI_SDI_LEN_DW GENMASK(9, 0)
>>>> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
>>>> b/drivers/gpu/drm/xe/xe_ring_ops.c
>>>> index 5f15360d14bf..189e764e3914 100644
>>>> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
>>>> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>>>> @@ -169,6 +169,20 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
>>>> dw[i++] = upper_32_bits(addr);
>>>> dw[i++] = lower_32_bits(value);
>>>> dw[i++] = upper_32_bits(value);
>>>> + dw[i++] = MI_SEMAPHORE_WAIT |
>>>> + MI_SEMAPHORE_POLL |
>>>> + MI_SEMAPHORE_SAD_EQ_SDD;
>>>> + dw[i++] = lower_32_bits(value);
>>>> + dw[i++] = lower_32_bits(addr);
>>>> + dw[i++] = upper_32_bits(addr);
>>>> + dw[i++] = 0;
>>>> + dw[i++] = MI_SEMAPHORE_WAIT |
>>>> + MI_SEMAPHORE_POLL |
>>>> + MI_SEMAPHORE_SAD_EQ_SDD;
>>>> + dw[i++] = upper_32_bits(value);
>>>> + dw[i++] = lower_32_bits(addr + 4);
>>>> + dw[i++] = upper_32_bits(addr);
>>>> + dw[i++] = 0;
>>>>
>>>> return i;
>>>> }
>>>> --
>>>> 2.43.0
>>>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/1] drm/xe: serialize store_data and user_interrupt for ufence wait
2025-08-15 21:28 ` Yang, Fei
@ 2025-09-03 15:09 ` Matt Roper
0 siblings, 0 replies; 11+ messages in thread
From: Matt Roper @ 2025-09-03 15:09 UTC (permalink / raw)
To: Yang, Fei
Cc: Brost, Matthew, intel-xe@lists.freedesktop.org, De Marchi, Lucas
On Fri, Aug 15, 2025 at 09:28:32PM +0000, Yang, Fei wrote:
> > On Fri, Aug 15, 2025 at 03:03:33PM -0600, Yang, Fei wrote:
> >>> On Tue, Aug 12, 2025 at 11:28:46AM -0700, fei.yang@intel.com wrote:
> >>>> From: Fei Yang <fei.yang@intel.com>
> >>>>
> >>>> Quote BSpec, MI_STORE_DATA_IMM "simply initiates the write
> >>>> operation with command execution proceeding normally. Although the
> >>>> write operation is guaranteed to complete eventually, there is no
> >>>> mechanism to synchronize command execution with the completion (or
> >>>> even
> >>>> initiation) of these operations."
> >>>
> >>> Can we not just use update emit_store_imm_ppgtt_posted to use
> >>> MI_FLUSH_IMM + a PPGTT address? I think we can get rid of prior flush added in 3ad7d18c5dad7?
> >>>
> >>> According to bspec 45725 for MI_FLUSH_IMM:
> >>>
> >>> 'Usage note: After this command is completed with a Store DWord
> >>> enabled, CPU access to graphics memory willbe coherent (assuming the
> >>> Render Cache flush is not inhibited).'
> >>
> >> We already have a MI_FLUSH_DW in between the MI_STORE_DATA_IMM and
> >> MI_USER_INTERRUPT (See __emit_job_gen12_simple), but the issue was
> >> still reporduced.
> >>
> >
> > That is not what I'm suggesting. I'm suggesting convert emit_store_imm_ppgtt_posted
> > to use a MI_FLUSH_DW intruction rather than MI_STORE_DATA_IMM.
>
> Oh, sorry I misunderstood. Yes, that looks promising. At least the BSpec
> says CPU access would be coherent, but I'm not sure what would happen
> in the case where the write is triggering a page fault. Will give it a
> shot and send a different patch if it works.
Doesn't emit_store_imm_ppgtt_posted() get called on RCS/CCS engines?
MI_FLUSH_DW isn't supported on those engines (only BCS/VCS/VECS; you'd
need to use a PIPE_CONTROL instead for RCS/CCS).
Matt
>
> -Fei
>
> > Matt
> >
> >> static int emit_flush_imm_ggtt(u32 addr, u32 value, u32 flags, u32
> >> *dw, int i) {
> >> dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
> >> flags;
> >> dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
> >> dw[i++] = 0;
> >> dw[i++] = value;
> >>
> >> return i;
> >> }
> >>
> >>> Matt
> >>>
> >>>> The KMD currently emit MI_STORE_DATA_IMM and MI_USER_INTERRUPT
> >>>> consecutively to implement user fence. However, according to the
> >>>> BSpec, the data write operation is not guaranteed to be completed
> >>>> when triggering the interrupt, that would cause the
> >>>> xe_wait_user_fence_ioctl to wait until the full user specified
> >>>> timeout is reached before checking the fence value again. Great
> >>>> performance degradation has been observed in IGT xe_exec_fault_mode
> >>>> test cases due to this unnecessary wait. The worst case is that if
> >>>> user set the timeout to MAX_INT32, the wait could end up being a hang until some other random program triggers a user interrupt to wake it up.
> >>>> A semaphore wait is added right after the data write to avoid the
> >>>> unexpected wait.
> >>>>
> >>>> Signed-off-by: Fei Yang <fei.yang@intel.com>
> >>>> ---
> >>>> drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 11 +++++++++++
> >>>> drivers/gpu/drm/xe/xe_ring_ops.c | 14 ++++++++++++++
> >>>> 2 files changed, 25 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >>>> b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >>>> index c47b290e0e9f..1c9e7b35c665 100644
> >>>> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >>>> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> >>>> @@ -34,6 +34,17 @@
> >>>> #define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
> >>>> #define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
> >>>>
> >>>> +#define MI_SEMAPHORE_WAIT (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5))
> >>>> +#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16)
> >>>> +#define MI_SEMAPHORE_POLL REG_BIT(15)
> >>>> +#define MI_SEMAPHORE_COMP_OP GENMASK(14, 12)
> >>>> +#define MI_SEMAPHORE_SAD_GT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 0)
> >>>> +#define MI_SEMAPHORE_SAD_GTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 1)
> >>>> +#define MI_SEMAPHORE_SAD_LT_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 2)
> >>>> +#define MI_SEMAPHORE_SAD_LTE_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 3)
> >>>> +#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 4)
> >>>> +#define MI_SEMAPHORE_SAD_NEQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_COMP_OP, 5)
> >>>> +
> >>>> #define MI_STORE_DATA_IMM __MI_INSTR(0x20)
> >>>> #define MI_SDI_GGTT REG_BIT(22)
> >>>> #define MI_SDI_LEN_DW GENMASK(9, 0)
> >>>> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
> >>>> b/drivers/gpu/drm/xe/xe_ring_ops.c
> >>>> index 5f15360d14bf..189e764e3914 100644
> >>>> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> >>>> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> >>>> @@ -169,6 +169,20 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
> >>>> dw[i++] = upper_32_bits(addr);
> >>>> dw[i++] = lower_32_bits(value);
> >>>> dw[i++] = upper_32_bits(value);
> >>>> + dw[i++] = MI_SEMAPHORE_WAIT |
> >>>> + MI_SEMAPHORE_POLL |
> >>>> + MI_SEMAPHORE_SAD_EQ_SDD;
> >>>> + dw[i++] = lower_32_bits(value);
> >>>> + dw[i++] = lower_32_bits(addr);
> >>>> + dw[i++] = upper_32_bits(addr);
> >>>> + dw[i++] = 0;
> >>>> + dw[i++] = MI_SEMAPHORE_WAIT |
> >>>> + MI_SEMAPHORE_POLL |
> >>>> + MI_SEMAPHORE_SAD_EQ_SDD;
> >>>> + dw[i++] = upper_32_bits(value);
> >>>> + dw[i++] = lower_32_bits(addr + 4);
> >>>> + dw[i++] = upper_32_bits(addr);
> >>>> + dw[i++] = 0;
> >>>>
> >>>> return i;
> >>>> }
> >>>> --
> >>>> 2.43.0
> >>>>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-09-03 15:09 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
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2025-08-12 18:28 [PATCH 0/1] drm/xe: serialize store_data and user_interrupt for ufence wait fei.yang
2025-08-12 18:28 ` [PATCH 1/1] " fei.yang
2025-08-12 20:07 ` Matthew Brost
2025-08-15 21:03 ` Yang, Fei
2025-08-15 21:08 ` Matthew Brost
2025-08-15 21:28 ` Yang, Fei
2025-09-03 15:09 ` Matt Roper
2025-08-13 19:53 ` ✗ CI.checkpatch: warning for drm/xe: serialize store_data and user_interrupt for ufence wait (rev2) Patchwork
2025-08-13 19:54 ` ✓ CI.KUnit: success " Patchwork
2025-08-13 20:56 ` ✓ Xe.CI.BAT: " Patchwork
2025-08-13 22:02 ` ✗ Xe.CI.Full: failure " Patchwork
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