From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0741CAC580 for ; Sat, 6 Sep 2025 05:50:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 76B1D10E307; Sat, 6 Sep 2025 05:50:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aKxhtNFu"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42C0010E1A3 for ; Sat, 6 Sep 2025 05:50:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757137853; x=1788673853; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=35nVItM6+PWxgj+S+BdJjL3V0FK37BcLHar9T1fsafY=; b=aKxhtNFuRUdEUbnPH+QMY+vE08fQGtQYFOU/qW6lPmLBTHzDqocloocG +HypObV+lLLU8MafkTs7Ml1bkeKlR34IFOyMenNnQA0RR/rVxRSt1NNw5 NhtHe4UoDIpjmAQ8ZFVYGtFOY3NVuzjYA5Mo2L7QqXkFkpPOPOX53Za92 8/RZgtSnQSCnbJIwUh+f2y9YWa1iOUXnLoCJ5/OD3ktKFV3qEfu+frcAx y1z74ZKsWJ3a2BuFo/B8jIMN1+YXaueWPvEkcfd6fHdXzEnNZ4vj4wH2q +QUpTSzKJhc4LT7WYIv7GbMgySgslaZrtN9IkBej/IW7nCts+4OKbZbNK g==; X-CSE-ConnectionGUID: 8w8P9GqUTAusGo10ri1YZQ== X-CSE-MsgGUID: cCbjruScQB2nbcoOcV1LkQ== X-IronPort-AV: E=McAfee;i="6800,10657,11544"; a="59628647" X-IronPort-AV: E=Sophos;i="6.18,243,1751266800"; d="scan'208";a="59628647" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 22:50:53 -0700 X-CSE-ConnectionGUID: YcIHSQ8fQAKjuYBBDzhAOg== X-CSE-MsgGUID: wutRvR9lSMGqAqJyfdwsiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,243,1751266800"; d="scan'208";a="203262843" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2025 22:50:53 -0700 From: Lucas De Marchi To: intel-xe@lists.freedesktop.org Cc: Lucas De Marchi , Stuart Summers , Matt Roper , Riana Tauro , Rodrigo Vivi , Umesh Nerlige Ramappa , Tvrtko Ursulin , Raag Jadav Subject: [PATCH v3 5/6] drm/xe/lrc: Allow to add user commands on context switch Date: Fri, 5 Sep 2025 22:50:33 -0700 Message-ID: <20250905-wa-bb-cmds-v3-5-3da2b7bdc73e@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250905-wa-bb-cmds-v3-0-3da2b7bdc73e@intel.com> References: <20250905-wa-bb-cmds-v3-0-3da2b7bdc73e@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.15-dev-b03c7 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" During validation it's useful to allows additional commands to be executed on context switch. Fetch the commands from configfs (to be added) and add them to the WA BB. Signed-off-by: Lucas De Marchi --- v2: Fix warning when building without configfs --- drivers/gpu/drm/xe/xe_configfs.c | 13 +++++++++++++ drivers/gpu/drm/xe/xe_configfs.h | 6 ++++++ drivers/gpu/drm/xe/xe_lrc.c | 25 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c index f42178a30383c..21fd153666db8 100644 --- a/drivers/gpu/drm/xe/xe_configfs.c +++ b/drivers/gpu/drm/xe/xe_configfs.c @@ -633,6 +633,19 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) return ret; } +/** + * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting + * @pdev: pci device + * + * Return: post_ctx_restore setting in configfs + */ +u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, + enum xe_engine_class class, + const u32 **cs) +{ + return 0; +} + int __init xe_configfs_init(void) { int ret; diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h index 1402e863b71c0..eff2645b5f593 100644 --- a/drivers/gpu/drm/xe/xe_configfs.h +++ b/drivers/gpu/drm/xe/xe_configfs.h @@ -8,6 +8,8 @@ #include #include +#include + struct pci_dev; #if IS_ENABLED(CONFIG_CONFIGFS_FS) @@ -17,6 +19,8 @@ void xe_configfs_check_device(struct pci_dev *pdev); bool xe_configfs_get_survivability_mode(struct pci_dev *pdev); u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev); bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev); +u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class, + const u32 **cs); #else static inline int xe_configfs_init(void) { return 0; } static inline void xe_configfs_exit(void) { } @@ -24,6 +28,8 @@ static inline void xe_configfs_check_device(struct pci_dev *pdev) { } static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; } static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; } static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; } +static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class, + const u32 **cs) { return 0; } #endif #endif diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 8f6c3ba478828..13e920a53e3a8 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -16,6 +16,7 @@ #include "regs/xe_lrc_layout.h" #include "xe_bb.h" #include "xe_bo.h" +#include "xe_configfs.h" #include "xe_device.h" #include "xe_drm_client.h" #include "xe_exec_queue_types.h" @@ -1102,6 +1103,29 @@ static ssize_t setup_timestamp_wa(struct xe_lrc *lrc, struct xe_hw_engine *hwe, return cmd - batch; } +static ssize_t setup_configfs_post_ctx_restore_bb(struct xe_lrc *lrc, + struct xe_hw_engine *hwe, + u32 *batch, size_t max_len) +{ + struct xe_device *xe = gt_to_xe(lrc->gt); + const u32 *user_batch; + u32 *cmd = batch; + u32 count; + + count = xe_configfs_get_ctx_restore_post_bb(to_pci_dev(xe->drm.dev), + hwe->class, &user_batch); + if (!count) + return 0; + + if (count > max_len) + return -ENOSPC; + + memcpy(cmd, user_batch, count * sizeof(u32)); + cmd += count; + + return cmd - batch; +} + static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc, struct xe_hw_engine *hwe, u32 *batch, size_t max_len) @@ -1203,6 +1227,7 @@ int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe { .setup = setup_timestamp_wa }, { .setup = setup_invalidate_state_cache_wa }, { .setup = setup_utilization_wa }, + { .setup = setup_configfs_post_ctx_restore_bb }, }; struct bo_setup_state state = { .lrc = lrc, -- 2.50.1