From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BB14CAC5BF for ; Wed, 24 Sep 2025 01:16:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71E7910E6AB; Wed, 24 Sep 2025 01:16:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mVs6BaFd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id F24F610E69D for ; Wed, 24 Sep 2025 01:16:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1758676571; x=1790212571; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=EAHqxdD9xafcbWVjczK42/Dz8kc+Yrla4ZrPNftXHeU=; b=mVs6BaFdX01y0BHRssOsKFebS/hTMrgRuRkozPBq3Vaiv1wYGgSWNRLS G6LT1lgR8eJ1RDimoVdSAzS8THYSTKr9cCyKGrFk/GPiRdNbASIJRLToF 9SULSEx59MGkUweK6jXoTEeIQMk8eNlB8jR0dHuVPDPRc//W1UWu2idxs 4mM0f7i//a1kZsJjSKS8YVjxfzY2KfyA8tJK0F3F6TnGAyBzzhhee4/he JHIsKji43lL8FWtBGvhbeKfSlQikaMEbeHvBd+21fufMz65hk1nacr9qJ 3MFx99v1bikvwyV7ioLaeIy8bZO7/aJZmTHIA3DiK0zMEMB+LVvEewvG1 Q==; X-CSE-ConnectionGUID: s+GsYNUvTsi81cdS3YrTmA== X-CSE-MsgGUID: NCSt+kkATOGvHPj8k+X+Og== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="60908277" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="60908277" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2025 18:16:11 -0700 X-CSE-ConnectionGUID: aVCmJx9PSeeciV3uNxcVGw== X-CSE-MsgGUID: L5ltzFHeS1GNpAUop36BzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,289,1751266800"; d="scan'208";a="207841805" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2025 18:16:10 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org Subject: [PATCH v2 24/34] drm/xe/vf: Start CTs before resfix VF post migration recovery Date: Tue, 23 Sep 2025 18:15:51 -0700 Message-Id: <20250924011601.888293-25-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250924011601.888293-1-matthew.brost@intel.com> References: <20250924011601.888293-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Before `resfix`, all CTs stuck in the H2G queue need to be squashed, as they may contain stale or invalid data. Starting the CTs clears all H2Gs in the queue. Any lost H2Gs are resubmitted by the GuC submission state machine. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 7 +++++ drivers/gpu/drm/xe/xe_guc_ct.c | 48 +++++++++++++++++++++++------ drivers/gpu/drm/xe/xe_guc_ct.h | 1 + 3 files changed, 46 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c index 2a077a98e92e..34e57f44fbf4 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c @@ -1214,6 +1214,11 @@ static int vf_post_migration_fixups(struct xe_gt *gt) return 0; } +static void vf_post_migration_rearm(struct xe_gt *gt) +{ + xe_guc_ct_restart(>->uc.guc.ct); +} + static void vf_post_migration_kickstart(struct xe_gt *gt) { xe_guc_submit_unpause(>->uc.guc); @@ -1263,6 +1268,8 @@ static void vf_post_migration_recovery(struct xe_gt *gt) if (err) goto fail; + vf_post_migration_rearm(gt); + err = vf_post_migration_notify_resfix_done(gt); if (err && err != -EAGAIN) goto fail; diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c index d4a132b81b86..fa55e9c9de3a 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.c +++ b/drivers/gpu/drm/xe/xe_guc_ct.c @@ -501,7 +501,7 @@ static void ct_exit_safe_mode(struct xe_guc_ct *ct) xe_gt_dbg(ct_to_gt(ct), "GuC CT safe-mode disabled\n"); } -int xe_guc_ct_enable(struct xe_guc_ct *ct) +static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register) { struct xe_device *xe = ct_to_xe(ct); struct xe_gt *gt = ct_to_gt(ct); @@ -513,17 +513,19 @@ int xe_guc_ct_enable(struct xe_guc_ct *ct) guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap); guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap); - err = guc_ct_ctb_h2g_register(ct); - if (err) - goto err_out; + if (needs_register) { + err = guc_ct_ctb_h2g_register(ct); + if (err) + goto err_out; - err = guc_ct_ctb_g2h_register(ct); - if (err) - goto err_out; + err = guc_ct_ctb_g2h_register(ct); + if (err) + goto err_out; - err = guc_ct_control_toggle(ct, true); - if (err) - goto err_out; + err = guc_ct_control_toggle(ct, true); + if (err) + goto err_out; + } guc_ct_change_state(ct, XE_GUC_CT_STATE_ENABLED); @@ -555,6 +557,32 @@ int xe_guc_ct_enable(struct xe_guc_ct *ct) return err; } +/** + * xe_guc_ct_restart() - Restart GuC CT + * @ct: the &xe_guc_ct + * + * Restart GuC CT to an empty state without issuing a CT register MMIO command. + * + * Return: 0 on success, or a negative errno on failure. + */ +int xe_guc_ct_restart(struct xe_guc_ct *ct) +{ + return __xe_guc_ct_start(ct, false); +} + +/** + * xe_guc_ct_enable() - Enable GuC CT + * @ct: the &xe_guc_ct + * + * Enable GuC CT to an empty state and issue a CT register MMIO command. + * + * Return: 0 on success, or a negative errno on failure. + */ +int xe_guc_ct_enable(struct xe_guc_ct *ct) +{ + return __xe_guc_ct_start(ct, true); +} + static void stop_g2h_handler(struct xe_guc_ct *ct) { cancel_work_sync(&ct->g2h_worker); diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h index 1e32a59817cc..506616ec1db0 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.h +++ b/drivers/gpu/drm/xe/xe_guc_ct.h @@ -15,6 +15,7 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct); int xe_guc_ct_init(struct xe_guc_ct *ct); int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct); int xe_guc_ct_enable(struct xe_guc_ct *ct); +int xe_guc_ct_restart(struct xe_guc_ct *ct); void xe_guc_ct_disable(struct xe_guc_ct *ct); void xe_guc_ct_stop(struct xe_guc_ct *ct); void xe_guc_ct_flush(struct xe_guc_ct *ct); -- 2.34.1