From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Subject: [PATCH v3 3/6] drm/i915/dp: Calculate DSC slice count based on per-slice peak throughput
Date: Wed, 24 Sep 2025 18:23:29 +0300 [thread overview]
Message-ID: <20250924152332.359768-4-imre.deak@intel.com> (raw)
In-Reply-To: <20250924152332.359768-1-imre.deak@intel.com>
Use the branch device's actual per-slice peak throughput to calculate
the minimum number of required DSC slices, falling back to the
hard-coded throughput values (as suggested by the DP Standard) if the
device's reported throughput value is 0.
For now use the minimum of the two throughput values, which is ok,
potentially resulting in a higher than required minimum slice count.
This doesn't change the current way of using the same minimum throughput
value regardless of the RGB/YUV output format used.
v2: Use drm helpers to query the throughput caps. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++----------
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2eab591a8ef56..f81bc39c26a72 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -96,11 +96,6 @@
#include "intel_vdsc.h"
#include "intel_vrr.h"
-/* DP DSC throughput values used for slice count calculations KPixels/s */
-#define DP_DSC_PEAK_PIXEL_RATE 2720000
-#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
-#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
-
/* Max DSC line buffer depth supported by HW. */
#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
@@ -1018,13 +1013,24 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
struct intel_display *display = to_intel_display(connector);
u8 min_slice_count, i;
int max_slice_width;
+ int tp_rgb_yuv444;
+ int tp_yuv422_420;
- if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
- min_slice_count = DIV_ROUND_UP(mode_clock,
- DP_DSC_MAX_ENC_THROUGHPUT_0);
- else
- min_slice_count = DIV_ROUND_UP(mode_clock,
- DP_DSC_MAX_ENC_THROUGHPUT_1);
+ tp_rgb_yuv444 = drm_dp_dsc_branch_max_slice_throughput(connector->dp.dsc_dpcd,
+ mode_clock, true);
+ tp_yuv422_420 = drm_dp_dsc_branch_max_slice_throughput(connector->dp.dsc_dpcd,
+ mode_clock, false);
+
+ /*
+ * TODO: Use the throughput value specific to the actual RGB/YUV
+ * format of the output.
+ * For now use the smaller of these, which is ok, potentially
+ * resulting in a higher than required minimum slice count.
+ * The RGB/YUV444 throughput value should be always either equal
+ * or smaller than the YUV422/420 value, but let's not depend on
+ * this assumption.
+ */
+ min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420));
/*
* Due to some DSC engine BW limitations, we need to enable second
--
2.49.1
next prev parent reply other threads:[~2025-09-24 15:24 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 15:23 [PATCH v3 0/6] drm/i915/dp: Work around a DSC pixel throughput issue Imre Deak
2025-09-24 15:23 ` [PATCH v3 1/6] drm/dp: Add quirk for Synaptics DSC throughput link-bpp limit Imre Deak
2025-09-24 15:23 ` [PATCH v3 2/6] drm/dp: Add helpers to query the branch DSC max throughput/line-width Imre Deak
2025-09-26 16:38 ` Ville Syrjälä
2025-09-26 18:37 ` Imre Deak
2025-09-24 15:23 ` Imre Deak [this message]
2025-09-24 15:23 ` [PATCH v3 4/6] drm/i915/dp: Pass DPCD device descriptor to intel_dp_get_dsc_sink_cap() Imre Deak
2025-09-24 15:23 ` [PATCH v3 5/6] drm/i915/dp: Verify branch devices' overall pixel throughput/line width Imre Deak
2025-09-24 15:23 ` [PATCH v3 6/6] drm/i915/dp: Handle Synaptics DSC throughput link-bpp quirk Imre Deak
2025-09-24 15:32 ` ✗ CI.checkpatch: warning for drm/i915/dp: Work around a DSC pixel throughput issue (rev4) Patchwork
2025-09-24 15:33 ` ✓ CI.KUnit: success " Patchwork
2025-09-24 16:07 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-24 20:12 ` ✗ Xe.CI.Full: failure " Patchwork
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