From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E27F9CCD182 for ; Mon, 29 Sep 2025 02:56:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97F7F10E3A7; Mon, 29 Sep 2025 02:56:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mzx92Oe+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id A041F10E20C for ; Mon, 29 Sep 2025 02:55:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759114553; x=1790650553; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=a05n6ugPT43R0aFOg7NRLne1EpTSqSYQr4hEGsCof3Q=; b=mzx92Oe+u9TkRUJVIjM9G7X+mXcxuOGx7Nh5djQDu6LGdvKBkZfYuiAS D4p8GxMPhvnihtzbWBT3WZjxcU/L6NYzbO5bZpNcO/TgMwWOfsGjbhnH4 Q+7PoeJNoM/PWyLJ4FH0ckOSPZeichRifxIaqHyJVbjNgUzrDBM5UY7iK f3F2PRvzPQxBe4pZUz7wEiksxkA1cmspJ9kLf02vZKxMkAngC+IFajqYR 133D3+H9LHsrFjDJ4qfWqoModB3jSgsADSGi66+bSCLvyOPKM7QZkZZoK XoyyDOeBvktFCKjR6vUUgnLCC43+5bztqWTEL9K3VLiyMq5ovYLLVX7wM Q==; X-CSE-ConnectionGUID: Dn6LxTyiTxe/rXHj8P8arw== X-CSE-MsgGUID: kX6lfwz3RdG7xhqG6d2Y1A== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="61398549" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="61398549" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2025 19:55:53 -0700 X-CSE-ConnectionGUID: xHDwEoDfRLmrRtTVHaljDg== X-CSE-MsgGUID: vKW5J9dlT+G202svHUWD4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,300,1751266800"; d="scan'208";a="182529283" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2025 19:55:52 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org Subject: [PATCH v3 33/36] drm/xe/vf: Use primary GT ordered work queue on media GT on PTL VF Date: Sun, 28 Sep 2025 19:55:39 -0700 Message-Id: <20250929025542.1486303-34-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250929025542.1486303-1-matthew.brost@intel.com> References: <20250929025542.1486303-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" VF CCS restore is a primary GT operation on which the media GT depends. Therefore, it doesn't make much sense to run these operations in parallel. To address this, point the media GT's ordered work queue to the primary GT's ordered work queue on platforms that require (PTL VFs) CCS restore as part of VF post-migration recovery. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_device_types.h | 2 ++ drivers/gpu/drm/xe/xe_gt.c | 16 ++++++++++------ drivers/gpu/drm/xe/xe_gt.h | 2 +- drivers/gpu/drm/xe/xe_pci.c | 6 +++++- drivers/gpu/drm/xe/xe_pci_types.h | 1 + drivers/gpu/drm/xe/xe_tile.c | 2 +- 6 files changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index a6c361db11d9..af92c8cd43b6 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -318,6 +318,8 @@ struct xe_device { u8 skip_mtcfg:1; /** @info.skip_pcode: skip access to PCODE uC */ u8 skip_pcode:1; + /** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */ + u8 needs_shared_vf_gt_wq:1; } info; /** @wa_active: keep track of active workarounds */ diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index 5f04d562604b..0c38cd30143c 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -72,7 +72,7 @@ static void gt_fini(struct drm_device *drm, void *arg) destroy_workqueue(gt->ordered_wq); } -struct xe_gt *xe_gt_alloc(struct xe_tile *tile) +struct xe_gt *xe_gt_alloc(struct xe_tile *tile, bool use_primary_wq) { struct xe_gt *gt; int err; @@ -82,12 +82,16 @@ struct xe_gt *xe_gt_alloc(struct xe_tile *tile) return ERR_PTR(-ENOMEM); gt->tile = tile; - gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", - WQ_MEM_RECLAIM); + if (use_primary_wq) { + gt->ordered_wq = tile->primary_gt->ordered_wq; + } else { + gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", + WQ_MEM_RECLAIM); - err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); - if (err) - return ERR_PTR(err); + err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); + if (err) + return ERR_PTR(err); + } return gt; } diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h index ee0239b2f48c..2e3898c18746 100644 --- a/drivers/gpu/drm/xe/xe_gt.h +++ b/drivers/gpu/drm/xe/xe_gt.h @@ -28,7 +28,7 @@ static inline bool xe_fault_inject_gt_reset(void) return IS_ENABLED(CONFIG_DEBUG_FS) && should_fail(>_reset_failure, 1); } -struct xe_gt *xe_gt_alloc(struct xe_tile *tile); +struct xe_gt *xe_gt_alloc(struct xe_tile *tile, bool use_primary_wq); int xe_gt_init_early(struct xe_gt *gt); int xe_gt_init(struct xe_gt *gt); void xe_gt_mmio_init(struct xe_gt *gt); diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 3f42b91efa28..25a1d96a68e7 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -347,6 +347,7 @@ static const struct xe_device_desc ptl_desc = { .has_sriov = true, .max_gt_per_tile = 2, .needs_scratch = true, + .needs_shared_vf_gt_wq = true, }; #undef PLATFORM @@ -598,6 +599,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.skip_mtcfg = desc->skip_mtcfg; xe->info.skip_pcode = desc->skip_pcode; xe->info.needs_scratch = desc->needs_scratch; + xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && xe_modparam.probe_display && @@ -766,7 +768,9 @@ static int xe_info_init(struct xe_device *xe, * Allocate and setup media GT for platforms with standalone * media. */ - tile->media_gt = xe_gt_alloc(tile); + tile->media_gt = xe_gt_alloc(tile, + xe->info.needs_shared_vf_gt_wq && + IS_SRIOV_VF(xe)); if (IS_ERR(tile->media_gt)) return PTR_ERR(tile->media_gt); diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index 9b9766a3baa3..b11bf6abda5b 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -48,6 +48,7 @@ struct xe_device_desc { u8 skip_guc_pc:1; u8 skip_mtcfg:1; u8 skip_pcode:1; + u8 needs_shared_vf_gt_wq:1; }; struct xe_graphics_desc { diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c index d49ba3401963..a982732a8056 100644 --- a/drivers/gpu/drm/xe/xe_tile.c +++ b/drivers/gpu/drm/xe/xe_tile.c @@ -149,7 +149,7 @@ int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id) if (err) return err; - tile->primary_gt = xe_gt_alloc(tile); + tile->primary_gt = xe_gt_alloc(tile, false); if (IS_ERR(tile->primary_gt)) return PTR_ERR(tile->primary_gt); -- 2.34.1