From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EA14CCD186 for ; Mon, 6 Oct 2025 10:45:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A2A0910E40D; Mon, 6 Oct 2025 10:45:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mn/a2VGy"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42E5510E314 for ; Mon, 6 Oct 2025 10:44:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759747493; x=1791283493; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=QchemB+dbthPl69R0Vee2yCUGUZbeMP/T4R9XXYuOnY=; b=mn/a2VGyDkuLV2bDr9s5JrCpKqhxYho4bsh/iCEaFI0k2tWu+gepIzyl uBFDymQ/a5iGfkRB/LaZJtQyiqJ/4h9uXAsoqpOTUb7n02vU8ai+UsvJ4 Uf4ETLnNy+bdeZbOfTK0riG3ydOSmyfBoJWO7dbd+Fv61zcIrwLorIri9 yJlH/QuMyMh9/r69BHXJ1L8cdFCRUMDKeytaaaqOnvGZ8FO5JSrKd7HFu 3LVb2S7NqTqInTMq77Dm6uW3ZxQM1fnKEpAbC2dtojeT4SSJNyMkwkF6J kP8kakX/CpuWXhjuVVZypNVWMq+2jHkEZ+I3YD/3lddmqToHAWxECu7X8 w==; X-CSE-ConnectionGUID: yXUQg3XDQEK+HSb/oi6aEA== X-CSE-MsgGUID: coLc2Si9QOynt4/0ToxV1g== X-IronPort-AV: E=McAfee;i="6800,10657,11573"; a="84546330" X-IronPort-AV: E=Sophos;i="6.18,319,1751266800"; d="scan'208";a="84546330" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 03:44:52 -0700 X-CSE-ConnectionGUID: Ma/P4jXkTNuw1xyZZ12aEw== X-CSE-MsgGUID: QhGI5w6zS9m6rkrTz+khvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,319,1751266800"; d="scan'208";a="203589328" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 03:44:51 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org Subject: [PATCH v5 17/30] drm/xe/vf: Flush and stop CTs in VF post migration recovery Date: Mon, 6 Oct 2025 03:44:32 -0700 Message-Id: <20251006104445.2210624-18-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251006104445.2210624-1-matthew.brost@intel.com> References: <20251006104445.2210624-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Flushing CTs (i.e., progressing all pending G2H messages) gives VF post-migration recovery an accurate view of which H2G messages the GuC has processed, enabling the GuC submission state machine to correctly rebuild all state. Also, stop all CT traffic, as the CT is not live during VF post-migration recovery. v3: - xe_guc_ct_flush_and_stop rename (Michal) - Drop extra GuC CT WQ wake up (Michal) Signed-off-by: Matthew Brost Reviewed-by: Michal Wajdeczko --- drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 1 + drivers/gpu/drm/xe/xe_guc_ct.c | 10 ++++++++++ drivers/gpu/drm/xe/xe_guc_ct.h | 1 + 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c index 7f703336d692..768ab33d2486 100644 --- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c +++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c @@ -1111,6 +1111,7 @@ static void vf_post_migration_shutdown(struct xe_gt *gt) gt->sriov.vf.migration.recovery_queued = false; spin_unlock_irq(>->sriov.vf.migration.lock); + xe_guc_ct_flush_and_stop(>->uc.guc.ct); xe_guc_submit_pause(>->uc.guc); } diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c index 3ac654cebc79..f67575b1ed79 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.c +++ b/drivers/gpu/drm/xe/xe_guc_ct.c @@ -574,6 +574,16 @@ void xe_guc_ct_disable(struct xe_guc_ct *ct) stop_g2h_handler(ct); } +/** + * xe_guc_ct_flush_and_stop - Flush and stop all processing of G2H / H2G + * @ct: the &xe_guc_ct + */ +void xe_guc_ct_flush_and_stop(struct xe_guc_ct *ct) +{ + receive_g2h(ct); + xe_guc_ct_stop(ct); +} + /** * xe_guc_ct_stop - Set GuC to stopped state * @ct: the &xe_guc_ct diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h index ca0ec938edac..02eaa452b400 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.h +++ b/drivers/gpu/drm/xe/xe_guc_ct.h @@ -17,6 +17,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct); int xe_guc_ct_enable(struct xe_guc_ct *ct); void xe_guc_ct_disable(struct xe_guc_ct *ct); void xe_guc_ct_stop(struct xe_guc_ct *ct); +void xe_guc_ct_flush_and_stop(struct xe_guc_ct *ct); void xe_guc_ct_fast_path(struct xe_guc_ct *ct); struct xe_guc_ct_snapshot *xe_guc_ct_snapshot_capture(struct xe_guc_ct *ct); -- 2.34.1