From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B13DCCD194 for ; Wed, 8 Oct 2025 18:05:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC98610E89B; Wed, 8 Oct 2025 18:05:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mDHOepis"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id E865710E88D for ; Wed, 8 Oct 2025 18:05:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759946710; x=1791482710; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=m8TjV0f6t5LuV0zzIa4416b4HM3pMFUwfMJhsoVlD+8=; b=mDHOepispd+YHZfXopelqaofpAsrbO1eRWoIz+uNGhGbiwhKWV/bPgRd GrqFSLpU+fWesV5b1/AFGejW2gQO55RErd2GitMudrDaAqvKY9smclc65 0zzFJtK4aRBnyh7GPml6x9OOUyM7gh6oQTE2fn7h/tqxjsjDt0/RjAZOP uqwnYZaXw/HDk1/2/B735UuvNbHfiQFHb4BBdAhc6z7MIN5DeB3KoT+fQ RMaJJ3Fr6FjFilJV/p6zO8YtW6UcE9+xGLmX+u98H22y/LCIssGSfOFmQ 9lmbW6NiNlmB9PlL2xVpB7Q2wvHqGq58EeuhJ14ylnkZY8SRWxvMNMPx/ A==; X-CSE-ConnectionGUID: ktaPM8G+RXuQH3SV3aG4mQ== X-CSE-MsgGUID: 7B3NhNCVS6eHySp0v7Ix4g== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="62067541" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="62067541" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2025 11:05:07 -0700 X-CSE-ConnectionGUID: isnCdeKsQhmSw8zkuKzGew== X-CSE-MsgGUID: 8RSxTiJBTnCwfGxEOBla5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,214,1754982000"; d="scan'208";a="217593749" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2025 11:05:07 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org Subject: [PATCH v9 31/34] drm/xe/vf: Use primary GT ordered work queue on media GT on PTL VF Date: Wed, 8 Oct 2025 11:04:57 -0700 Message-Id: <20251008180500.3261209-32-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251008180500.3261209-1-matthew.brost@intel.com> References: <20251008180500.3261209-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" VF CCS restore is a primary GT operation on which the media GT depends. Therefore, it doesn't make much sense to run these operations in parallel. To address this, point the media GT's ordered work queue to the primary GT's ordered work queue on platforms that require (PTL VFs) CCS restore as part of VF post-migration recovery. v7: - Remove bool from xe_gt_alloc (Lucas) v9: - Fix typo (Lucas) Signed-off-by: Matthew Brost Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/xe/xe_device_types.h | 2 ++ drivers/gpu/drm/xe/xe_gt.c | 18 ++++++++++++++---- drivers/gpu/drm/xe/xe_pci.c | 2 ++ drivers/gpu/drm/xe/xe_pci_types.h | 1 + 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index c66523bf4bf0..02c04ad7296e 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -334,6 +334,8 @@ struct xe_device { u8 skip_mtcfg:1; /** @info.skip_pcode: skip access to PCODE uC */ u8 skip_pcode:1; + /** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */ + u8 needs_shared_vf_gt_wq:1; } info; /** @wa_active: keep track of active workarounds */ diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index 6951fedd4350..d8e94fb8b9bd 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -67,7 +67,11 @@ struct xe_gt *xe_gt_alloc(struct xe_tile *tile) { - struct drm_device *drm = &tile_to_xe(tile)->drm; + struct xe_device *xe = tile_to_xe(tile); + struct drm_device *drm = &xe->drm; + bool shared_wq = xe->info.needs_shared_vf_gt_wq && tile->primary_gt && + IS_SRIOV_VF(xe); + struct workqueue_struct *ordered_wq; struct xe_gt *gt; gt = drmm_kzalloc(drm, sizeof(*gt), GFP_KERNEL); @@ -75,9 +79,15 @@ struct xe_gt *xe_gt_alloc(struct xe_tile *tile) return ERR_PTR(-ENOMEM); gt->tile = tile; - gt->ordered_wq = drmm_alloc_ordered_workqueue(drm, "gt-ordered-wq", WQ_MEM_RECLAIM); - if (IS_ERR(gt->ordered_wq)) - return ERR_CAST(gt->ordered_wq); + if (shared_wq && tile->primary_gt->ordered_wq) + ordered_wq = tile->primary_gt->ordered_wq; + else + ordered_wq = drmm_alloc_ordered_workqueue(drm, "gt-ordered-wq", + WQ_MEM_RECLAIM); + if (IS_ERR(ordered_wq)) + return ERR_CAST(ordered_wq); + + gt->ordered_wq = ordered_wq; return gt; } diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 3f42b91efa28..f8243622429d 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -347,6 +347,7 @@ static const struct xe_device_desc ptl_desc = { .has_sriov = true, .max_gt_per_tile = 2, .needs_scratch = true, + .needs_shared_vf_gt_wq = true, }; #undef PLATFORM @@ -598,6 +599,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.skip_mtcfg = desc->skip_mtcfg; xe->info.skip_pcode = desc->skip_pcode; xe->info.needs_scratch = desc->needs_scratch; + xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && xe_modparam.probe_display && diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index 9b9766a3baa3..b11bf6abda5b 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -48,6 +48,7 @@ struct xe_device_desc { u8 skip_guc_pc:1; u8 skip_mtcfg:1; u8 skip_pcode:1; + u8 needs_shared_vf_gt_wq:1; }; struct xe_graphics_desc { -- 2.34.1