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It might be worth splitting this into two patches since CURRENT_LRCA is something that's been around forever and can already be dumped unconditionally on existing platforms, whereas CSMQDEBUG is a new Xe3p register. Also, I think CSMQDEBUG dumping would probably make more sense to be included as part of the MQ patch series that Niranjana will be sending later; dumping this register doesn't really have any value outside the context of that other work. A couple more comments farther down... > > Cc: Niranjana Vishwanathapura > Cc: Matt Roper > Signed-off-by: Wang Xin > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/xe/regs/xe_engine_regs.h | 5 +++ > drivers/gpu/drm/xe/xe_guc_capture.c | 53 +++++++++++++++++++++++++++++++- > 2 files changed, 57 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h > index f4c3e1187a00a..7b6ec0cf78c85 100644 > --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h > @@ -141,6 +141,9 @@ > #define INHIBIT_SWITCH_UNTIL_PREEMPTED REG_BIT(31) > #define IDLE_DELAY REG_GENMASK(20, 0) > > +#define RING_CURRENT_LRCA(base) XE_REG((base) + 0x240) > +#define CURRENT_LRCA_VALID REG_BIT(0) > + > #define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED) > #define CTX_CTRL_PXP_ENABLE REG_BIT(10) > #define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8) > @@ -153,6 +156,8 @@ > #define GFX_DISABLE_LEGACY_MODE REG_BIT(3) > #define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13) > > +#define RING_CSMQDEBUG(base) XE_REG((base) + 0x2b0) > + > #define RING_TIMESTAMP(base) XE_REG((base) + 0x358) > > #define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4) > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c > index 243dad3e24185..265aa7b7614ce 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture.c > +++ b/drivers/gpu/drm/xe/xe_guc_capture.c > @@ -122,6 +122,7 @@ struct __guc_capture_parsed_output { > { RING_IPEHR(0), REG_32BIT, 0, 0, 0, "IPEHR"}, \ > { RING_INSTDONE(0), REG_32BIT, 0, 0, 0, "RING_INSTDONE"}, \ > { INDIRECT_RING_STATE(0), REG_32BIT, 0, 0, 0, "INDIRECT_RING_STATE"}, \ > + { RING_CURRENT_LRCA(0), REG_32BIT, 0, 0, 0, "CURRENT_LRCA"}, \ > { RING_ACTHD(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \ > { RING_ACTHD_UDW(0), REG_64BIT_HI_DW, 0, 0, 0, "ACTHD"}, \ > { RING_BBADDR(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \ > @@ -149,6 +150,9 @@ struct __guc_capture_parsed_output { > { SFC_DONE(2), 0, 0, 0, 0, "SFC_DONE[2]"}, \ > { SFC_DONE(3), 0, 0, 0, 0, "SFC_DONE[3]"} > > +#define XE3P_BASE_ENGINE_INSTANCE \ > + { RING_CSMQDEBUG(0), REG_32BIT, 0, 0, 0, "CSMQDEBUG"} > + > /* XE_LP Global */ > static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = { > COMMON_XELP_BASE_GLOBAL, > @@ -195,6 +199,36 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = { > COMMON_BASE_ENGINE_INSTANCE, > }; > > +/* Render / Compute Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > + XE3P_BASE_ENGINE_INSTANCE, > +}; > + > +/* Media Decode/Encode Per-Engine-Instance */ I'm also wondering if we really need to dump it for the vcs/vecs/gsc engines; although the register technically exists there, those engines don't actually support MQ so maybe it's only worth dumping on the CCS and BCS engines? > +static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > + XE3P_BASE_ENGINE_INSTANCE, > +}; > + > +/* Video Enhancement Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > + XE3P_BASE_ENGINE_INSTANCE, > +}; > + > +/* Blitter Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > + XE3P_BASE_ENGINE_INSTANCE, > +}; > + > +/* XE3P - GSC Per-Engine-Instance */ > +static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = { > + COMMON_BASE_ENGINE_INSTANCE, > + XE3P_BASE_ENGINE_INSTANCE, > +}; > + > /* > * Empty list to prevent warnings about unknown class/instance types > * as not all class/instance types have entries on all platforms. > @@ -245,6 +279,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = { > {} > }; > > + /* List of lists for graphic product version >= 3500 */ > +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = { > + MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0), > + MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > + MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO), > + MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO), > + MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > + MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER), > + MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER), > + MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), > + MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER), > + {} > +}; > static const char * const capture_list_type_names[] = { > "Global", > "Class", > @@ -292,7 +341,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc, > static const struct __guc_mmio_reg_descr_group * > guc_capture_get_device_reglist(struct xe_device *xe) > { > - if (GRAPHICS_VERx100(xe) >= 1255) > + if (GRAPHICS_VERx100(xe) >= 3500) Since there's no IP with a version of exactly 35.00, I'd just do "GRAPHICS_VER(xe) >= 35" to avoid any confusion. Also in the comment a little bit farther up, I'd replace the "graphic product version >= 3500" with "Xe3p and beyond." Matt > + return xe3p_lists; > + else if (GRAPHICS_VERx100(xe) >= 1255) > return xe_hpg_lists; > else > return xe_lp_lists; > > -- > 2.51.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation