From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ABA5CCD18E for ; Wed, 15 Oct 2025 04:09:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0888410E73A; Wed, 15 Oct 2025 04:09:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="k3Y9uXta"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9161C10E73A; Wed, 15 Oct 2025 04:09:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1760501364; x=1792037364; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XcxzaCdaVi0iCHsWtUBTfnmxDIcW7Q0TKi8JrQ9i5ro=; b=k3Y9uXtaYrxCpzDbEnQ9Nb3JkZkVIlvto0OYpQDP3cC4ZK7CUxB+mH3q MwvNnV6jpd+vLVogmtag53hddnUyowON6/LTEU3ZdDULvjZFN0K42zGgJ hXGD4rl04hBrsSo+BH8GW5RYsJxuG9C7E4EOJl8bV5uEwFNrrKfp2n0YQ CO2EOldv9LNYlkJ2TBUyxXrduBqI20RqbCAcV/UfUXta+4naL0uAXoT0U p6BC8JlIH0FWs6vrXL7Qga3LpewdJmMMsqyfYXJtEykQWMRaxSRPMldbo oU+lz3XfZ6xLFeY7xeASVwdZif6h9VSsZnffIqBHismxNialo9Cy1IqMj g==; X-CSE-ConnectionGUID: ld3hIQp5TQex9557RaR+eQ== X-CSE-MsgGUID: 4Zl2wHitRG+NY10HjthG0A== X-IronPort-AV: E=McAfee;i="6800,10657,11582"; a="66318992" X-IronPort-AV: E=Sophos;i="6.19,230,1754982000"; d="scan'208";a="66318992" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2025 21:09:24 -0700 X-CSE-ConnectionGUID: rsN3S0+FTLyUhrhNAjTqQA== X-CSE-MsgGUID: utt+2iyuQHqy4x3lB4u+QA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,230,1754982000"; d="scan'208";a="219196296" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by orviesa001.jf.intel.com with ESMTP; 14 Oct 2025 21:09:22 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com, uma.shankar@intel.com, gustavo.sousa@intel.com, lucas.demarchi@intel.com, Suraj Kandpal Subject: [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function Date: Wed, 15 Oct 2025 09:38:12 +0530 Message-Id: <20251015040817.3431297-21-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251015040817.3431297-1-suraj.kandpal@intel.com> References: <20251015040817.3431297-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Define function to compare the state and if mismatch is detected dump both the states. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 33 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_lt_phy.c | 30 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.h | 6 ++++ 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d5b2612d4ec2..b05f70582788 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -99,6 +99,7 @@ #include "intel_hdmi.h" #include "intel_hotplug.h" #include "intel_link_bw.h" +#include "intel_lt_phy.h" #include "intel_lvds.h" #include "intel_lvds_regs.h" #include "intel_modeset_setup.h" @@ -4963,6 +4964,24 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI); } +static void +pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset, + const struct intel_crtc *crtc, + const char *name, + const struct intel_lt_phy_pll_state *a, + const struct intel_lt_phy_pll_state *b) +{ + struct intel_display *display = to_intel_display(crtc); + char *chipname = "LTPHY"; + + pipe_config_mismatch(p, fastset, crtc, name, chipname); + + drm_printf(p, "expected:\n"); + intel_lt_phy_dump_hw_state(display, a); + drm_printf(p, "found:\n"); + intel_lt_phy_dump_hw_state(display, b); +} + bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, @@ -5087,6 +5106,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_PLL_LT(name) do { \ + if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \ + &pipe_config->name)) { \ + pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \ + ¤t_config->name, \ + &pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_TIMINGS(name) do { \ PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ PIPE_CONF_CHECK_I(name.crtc_htotal); \ @@ -5311,7 +5340,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_PLL(dpll_hw_state); /* FIXME convert MTL+ platforms over to dpll_mgr */ - if (DISPLAY_VER(display) >= 14) + if (HAS_LT_PHY(display)) + PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll); + else if (DISPLAY_VER(display) >= 14) PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); PIPE_CONF_CHECK_X(dsi_pll.ctrl); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index f1e41f009bb5..0be4aad0efcc 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1843,6 +1843,36 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, intel_lt_phy_transaction_end(encoder, wakeref); } +void intel_lt_phy_dump_hw_state(struct intel_display *display, + const struct intel_lt_phy_pll_state *hw_state) +{ + int i, j; + + drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n"); + for (i = 0; i < 3; i++) { + drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n", + i, hw_state->config[i]); + } + + for (i = 0; i <= 12; i++) + for (j = 3; j >= 0; j--) + drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n", + i, j, hw_state->data[i][j]); +} + +bool +intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, + const struct intel_lt_phy_pll_state *b) +{ + if (memcmp(&a->config, &b->config, sizeof(a->config)) != 0) + return false; + + if (memcmp(&a->data, &b->data, sizeof(a->data)) != 0) + return false; + + return true; +} + void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h index 6e67ae78801c..e93e5becc316 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h @@ -8,6 +8,7 @@ #include +struct intel_display; struct intel_encoder; struct intel_crtc_state; struct intel_lt_phy_pll_state; @@ -22,6 +23,11 @@ int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_lt_phy_dump_hw_state(struct intel_display *display, + const struct intel_lt_phy_pll_state *hw_state); +bool +intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, + const struct intel_lt_phy_pll_state *b); void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); -- 2.34.1