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This created latency on SW stack. > > This feature adds support to generate completion interrupt from GPGPU > walker which does not support MSIx and avoid software using Pipe control > drain/idle latency. > > The only thing needed for the kernel driver to do here is to wakeup the > thread waiting on the ufence, which is already handled by the irq > handler. > > Suggested-by: Himal Prasad Ghimiray > Signed-off-by: S A Muqthyar Ahmed > Signed-off-by: Lucas De Marchi Digging into this more, I think the implementation is correct, but I think we could still expand the commit message a little bit more to explain how/when this winds up getting used. The description above left me uncertain whether these new interrupts are opt-in on a per-walker basis, or whether the hardware was going to start unconditionally generating interrupts for every walker's completion. After looking through the bspec, it looks like the interrupts here are only generated for COMPUTE_WALKER_2 instructions (not COMPUTE_WALKER) if specifically requested via the flag in the POST_SYNC_DATA_2 substructure's dw0[3]. So with a minor clarification to the commit message that the interrupts we're enabling here are something userspace can opt into on a per-walker basis, Bspec: 62346, 74334 Reviewed-by: Matt Roper Matt > --- > v2: Rebase on split mask per engine class > --- > drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 + > drivers/gpu/drm/xe/xe_irq.c | 6 ++++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h > index 815d5e3d22099..2f97662d958de 100644 > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h > @@ -85,6 +85,7 @@ > #define GSC_ER_COMPLETE REG_BIT(5) > #define GT_FLUSH_COMPLETE_INTERRUPT REG_BIT(4) > #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) > +#define GT_COMPUTE_WALKER_INTERRUPT REG_BIT(2) > #define GT_MI_USER_INTERRUPT REG_BIT(0) > > /* irqs for OTHER_KCR_INSTANCE */ > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c > index 8f2c8d3ae5f8a..e5ed0242f7b1d 100644 > --- a/drivers/gpu/drm/xe/xe_irq.c > +++ b/drivers/gpu/drm/xe/xe_irq.c > @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt) > if (xe_device_uc_enabled(xe)) { > common_mask = GT_MI_USER_INTERRUPT | > GT_FLUSH_COMPLETE_INTERRUPT; > + > + /* Enable Compute Walker Interrupt for non-MSIX platforms */ > + if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) { > + rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT; > + ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT; > + } > } else { > common_mask = GT_MI_USER_INTERRUPT | > GT_CS_MASTER_ERROR_INTERRUPT | > > -- > 2.51.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation