From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: matthew.d.roper@intel.com, Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [PATCH 0/2] Xe3p_XPC Steering Updates
Date: Tue, 21 Oct 2025 15:45:54 -0700 [thread overview]
Message-ID: <20251021224556.437970-1-matthew.d.roper@intel.com> (raw)
A late-breaking spec update has changed some details related to MCR
register steering for PSMI register ranges, and has supplied missing
information related to L3BANK and NODE MCR register ranges. Based on
the new spec details (and some offline discussion with the hardware
team), make the necessary adjustments to the driver's MCR code.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Matt Roper (2):
drm/xe/xe3p_xpc: Treat all PSMI MCR ranges as "INSTANCE0"
drm/xe/xe3p_xpc: Add MCR steering for NODE and L3BANK ranges
drivers/gpu/drm/xe/xe_gt_mcr.c | 36 ++++++++++++++++++-----------
drivers/gpu/drm/xe/xe_gt_topology.c | 7 ++++++
drivers/gpu/drm/xe/xe_gt_topology.h | 2 ++
drivers/gpu/drm/xe/xe_gt_types.h | 9 +-------
4 files changed, 33 insertions(+), 21 deletions(-)
--
2.51.0
next reply other threads:[~2025-10-21 22:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 22:45 Matt Roper [this message]
2025-10-21 22:45 ` [PATCH 1/2] drm/xe/xe3p_xpc: Treat all PSMI MCR ranges as "INSTANCE0" Matt Roper
2025-10-23 20:29 ` Lucas De Marchi
2025-10-21 22:45 ` [PATCH 2/2] drm/xe/xe3p_xpc: Add MCR steering for NODE and L3BANK ranges Matt Roper
2025-10-23 21:52 ` Lucas De Marchi
2025-10-21 23:38 ` ✓ CI.KUnit: success for Xe3p_XPC Steering Updates Patchwork
2025-10-22 0:17 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 3:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-23 23:28 ` Matt Roper
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