From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 456A7CCF9E2 for ; Wed, 22 Oct 2025 07:30:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E1B9610E6D0; Wed, 22 Oct 2025 07:30:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="Op52IPLn"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 068D310E6D0 for ; Wed, 22 Oct 2025 07:30:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Sender:Reply-To:Cc:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ulo3FHPVr8l0LPZSlhb1ZuC1WDPeRMLs8MPRk6RBBiM=; b=Op52IPLnyhcADtCncmwJsiAIPu s1qoc/sYWN0Q3tYZeupEy4ZwwHFPYDZKNPXUN5ov6/xevzxWF/W5qd3Mnupga5ZC8U/XGOFDyR6Q9 nfkOG+QeJbcE/E3KDoWrWQBa1HfVFYuZ4P5Pu6oVXbFwMcII7ljqGtUEdT+G/Jlx2whjwJ0/GP9FT oPmYId8KilTsZwPWZToVldkkDcj/K76WiBEzbAOz/ClWN8ARUpJXZo9f0QSNMMRF/8msPR+euF0V2 6TYx0xbts5x+XKgDzBsLhKtS4zFrK/T3cv2L22iSLwlLKF4CPJikw9AuW5+303KFh4Ly5gTK3EybS OyKKlZtQ==; Received: from [90.242.12.242] (helo=localhost) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_SECP256R1__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1vBTIV-00CswA-Ab for ; Wed, 22 Oct 2025 09:30:15 +0200 From: Tvrtko Ursulin To: intel-xe@lists.freedesktop.org Subject: [CI 06/13] drm/xe/xelp: Wait for AuxCCS invalidation to complete Date: Wed, 22 Oct 2025 08:29:58 +0100 Message-ID: <20251022073010.71285-7-tvrtko.ursulin@igalia.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20251022073010.71285-1-tvrtko.ursulin@igalia.com> References: <20251022073010.71285-1-tvrtko.ursulin@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On AuxCCS platforms we need to wait for AuxCCS invalidations to complete. Signed-off-by: Tvrtko Ursulin Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 6 ++++++ drivers/gpu/drm/xe/xe_ring_ops.c | 9 ++++++++- drivers/gpu/drm/xe/xe_ring_ops_types.h | 2 +- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h index c47b290e0e9f..49d8ffd026d5 100644 --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h @@ -81,4 +81,10 @@ #define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0) #define MI_SET_APPID_SESSION_ID(x) REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x) +#define MI_SEMAPHORE_WAIT_TOKEN (__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */ +#define MI_SEMAPHORE_REGISTER_POLL REG_BIT(16) +#define MI_SEMAPHORE_POLL REG_BIT(15) +#define MI_SEMAPHORE_CMP_OP_MASK REG_GENMASK(14, 12) +#define MI_SEMAPHORE_SAD_EQ_SDD REG_FIELD_PREP(MI_SEMAPHORE_CMP_OP_MASK, 4) + #endif diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index d226d3228199..071c45abda2a 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -56,7 +56,14 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg, dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN; dw[i++] = reg.addr + gt->mmio.adj_offset; dw[i++] = AUX_INV; - dw[i++] = MI_NOOP; + dw[i++] = MI_SEMAPHORE_WAIT_TOKEN | + MI_SEMAPHORE_REGISTER_POLL | + MI_SEMAPHORE_POLL | + MI_SEMAPHORE_SAD_EQ_SDD; + dw[i++] = 0; + dw[i++] = reg.addr + gt->mmio.adj_offset; + dw[i++] = 0; + dw[i++] = 0; return i; } diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h index 477dc7defd72..1197fc0bf2af 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops_types.h +++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h @@ -8,7 +8,7 @@ struct xe_sched_job; -#define MAX_JOB_SIZE_DW 70 +#define MAX_JOB_SIZE_DW 74 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4) /** -- 2.48.0