From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBCAFCCD1AB for ; Wed, 22 Oct 2025 07:33:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E70D10E6F3; Wed, 22 Oct 2025 07:33:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="VZPKFbl5"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C73F10E6F0 for ; Wed, 22 Oct 2025 07:32:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Sender:Reply-To:Cc:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=PRukJI9ECetCtQS9HDppqeIhQz7ykEvUPElMRumDSFc=; b=VZPKFbl59GOORHYesoRAsO65TM kdWG46i78bi1RnyDvFqzBSWb/7XwK7TLkkDgurtwzAu+z/HL/EOZUuW5WjMwbMCilNGWSI4iQXv5o 0/JuFeXo2jiMPziha8MCcX6+JDkFs3fU5Mwshq02M77Qt5LMPwubsI3vrhlF9tyXhQQbb0RPbGSUc cnzz4l5HNiEwcTiNTd7Oj09W6LlDJQ85tD8qNs5DOApzvgXXglH/85FlWb2lV/HCDkR/yEB4qk/H3 RBsvna7hmze257wpjKzIPUkmgt4GXGLZZPjYgLiDIpcwYdpAjQoYHynBDHpdPEEUskIQj3EFq0xCv nrZiS8pg==; Received: from [90.242.12.242] (helo=localhost) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_SECP256R1__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1vBTL2-00Ct1X-PB for ; Wed, 22 Oct 2025 09:32:52 +0200 From: Tvrtko Ursulin To: intel-xe@lists.freedesktop.org Subject: [CI 13/14] drm/xe/display: Add support for AuxCCS Date: Wed, 22 Oct 2025 08:32:38 +0100 Message-ID: <20251022073241.71401-14-tvrtko.ursulin@igalia.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20251022073241.71401-1-tvrtko.ursulin@igalia.com> References: <20251022073241.71401-1-tvrtko.ursulin@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add support for mapping the auxiliary CCS buffer into the DPT page tables. This will allow for more power efficiency by enabling the render compression frame buffer modifiers such as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS in a following patch. We do this by refactoring the code a bit so handling for the linear auxiliary frame buffer can be added in a tidy way. Also replace some hardcoded constants. Signed-off-by: Tvrtko Ursulin Cc: Juha-Pekka Heikkila Cc: Michael J. Ruhl --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 111 ++++++++++++++++++------- 1 file changed, 81 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 02e069df5b73..5a5869422d02 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -53,33 +53,94 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ *dpt_ofs = ALIGN(*dpt_ofs, 4096); } +static unsigned int +write_dpt_padding(struct iosys_map *map, unsigned int dest, unsigned int pad) +{ + /* The DE ignores the PTEs for the padding tiles */ + return dest + pad * sizeof(u64); +} + +static unsigned int +write_dpt_remapped_linear(struct xe_bo *bo, struct iosys_map *map, + unsigned int dest, + const struct intel_remapped_plane_info *plane) +{ + struct xe_device *xe = xe_bo_device(bo); + struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; + const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, + xe->pat.idx[XE_CACHE_NONE]); + unsigned int offset = plane->offset * XE_PAGE_SIZE; + unsigned int size = plane->size; + + while (size--) { + u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE); + + iosys_map_wr(map, dest, u64, addr | pte); + dest += sizeof(u64); + offset += XE_PAGE_SIZE; + } + + return dest; +} + +static unsigned int +write_dpt_remapped_tiled(struct xe_bo *bo, struct iosys_map *map, + unsigned int dest, + const struct intel_remapped_plane_info *plane) +{ + struct xe_device *xe = xe_bo_device(bo); + struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; + const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, + xe->pat.idx[XE_CACHE_NONE]); + unsigned int offset, column, row; + + for (row = 0; row < plane->height; row++) { + offset = (plane->offset + plane->src_stride * row) * + XE_PAGE_SIZE; + + for (column = 0; column < plane->width; column++) { + u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE); + + iosys_map_wr(map, dest, u64, addr | pte); + dest += sizeof(u64); + offset += XE_PAGE_SIZE; + } + + dest = write_dpt_padding(map, dest, + plane->dst_stride - plane->width); + } + + return dest; +} + static void -write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, - u32 bo_ofs, u32 width, u32 height, u32 src_stride, - u32 dst_stride) +write_dpt_remapped(struct xe_bo *bo, + const struct intel_remapped_info *remap_info, + struct iosys_map *map) { - struct xe_device *xe = xe_bo_device(bo); - struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; - u32 column, row; - u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); + unsigned int i, dest = 0; - for (row = 0; row < height; row++) { - u32 src_idx = src_stride * row + bo_ofs; + for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++) { + const struct intel_remapped_plane_info *plane = + &remap_info->plane[i]; - for (column = 0; column < width; column++) { - u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE); - iosys_map_wr(map, *dpt_ofs, u64, pte | addr); + if (!plane->width && !plane->height && !plane->linear) + continue; - *dpt_ofs += 8; - src_idx++; + if (remap_info->plane_alignment) { + const unsigned int index = dest / sizeof(u64); + const unsigned int pad = + ALIGN(index, remap_info->plane_alignment) - + index; + + dest = write_dpt_padding(map, dest, pad); } - /* The DE ignores the PTEs for the padding tiles */ - *dpt_ofs += (dst_stride - width) * 8; + if (plane->linear) + dest = write_dpt_remapped_linear(bo, map, dest, plane); + else + dest = write_dpt_remapped_tiled(bo, map, dest, plane); } - - /* Align to next page */ - *dpt_ofs = ALIGN(*dpt_ofs, 4096); } static void gt_flush_ggtt_writes(struct xe_gt *gt) @@ -195,17 +256,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr); } } else if (view->type == I915_GTT_VIEW_REMAPPED) { - const struct intel_remapped_info *remap_info = &view->remapped; - u32 i, dpt_ofs = 0; - - for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++) - write_dpt_remapped(bo, &dpt->vmap, &dpt_ofs, - remap_info->plane[i].offset, - remap_info->plane[i].width, - remap_info->plane[i].height, - remap_info->plane[i].src_stride, - remap_info->plane[i].dst_stride); - + write_dpt_remapped(bo, &view->remapped, &dpt->vmap); } else { const struct intel_rotation_info *rot_info = &view->rotated; u32 i, dpt_ofs = 0; -- 2.48.0