From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A6B8CCD1BC for ; Wed, 22 Oct 2025 07:32:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2994F10E6EA; Wed, 22 Oct 2025 07:32:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="nRhc4bKB"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 371B510E6E7 for ; Wed, 22 Oct 2025 07:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Sender:Reply-To:Cc:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=FwmfcokZ4ZaQqTRZGBZV42s2AdFDc1y1OXNMz7xdA5k=; b=nRhc4bKBoYsjM/dsZFZlT7JFo8 ArdeV5/sHyrCasJd1XNUiFK/B4kVIa/YyFmzCjN7Ptwm6EHJvpTA9ypZXtrKcO8QUQ+zztX5swDS5 LQqaeLagJn/bf/eRZlj5jJr8jfzZlQnlmee8qR2n3a/GjFOryNvv4hlqS80LInfuVoSZbN9R8nP/V FwSQddvT1pG6PHV7j2xuSLCA3E49G+TRPWn52pyO/Pqe2Io58YpK1gUIhPypkYJu/hdvKTQizdeKw s1DVMR+Fds8zKTR1LBLN4BxGc8xMj9DWeRXvCYEI+SHJFjbNyoFyL3BOWsY6JqhxW4lI7Xe28RG8M qR5t1uDA==; Received: from [90.242.12.242] (helo=localhost) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_SECP256R1__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1vBTKu-00Ct0j-E3 for ; Wed, 22 Oct 2025 09:32:44 +0200 From: Tvrtko Ursulin To: intel-xe@lists.freedesktop.org Subject: [CI 03/14] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Date: Wed, 22 Oct 2025 08:32:28 +0100 Message-ID: <20251022073241.71401-4-tvrtko.ursulin@igalia.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20251022073241.71401-1-tvrtko.ursulin@igalia.com> References: <20251022073241.71401-1-tvrtko.ursulin@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" According to i915 commit ad8ebf12217e ("drm/i915/gt: Ensure memory quiesced before invalidation") quiescing of the memory traffic is required before invalidating the AuxCCS tables. Add an extra pipe control flush to achieve that. Signed-off-by: Tvrtko Ursulin Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_ring_ops.c | 10 +++++++++- drivers/gpu/drm/xe/xe_ring_ops_types.h | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index 15fc4010a710..f384c9968859 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -363,12 +363,20 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, struct xe_gt *gt = job->q->gt; struct xe_device *xe = gt_to_xe(gt); bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); + const bool aux_ccs = has_aux_ccs(xe); u32 mask_flags = 0; *head = lrc->ring.tail; i = emit_copy_timestamp(lrc, dw, i); + /* + * On AuxCCS platforms the invalidation of the Aux table requires + * quiescing the memory traffic beforehand. + */ + if (aux_ccs) + i = emit_render_cache_flush(job, dw, i); + dw[i++] = preparser_disable(true); if (lacks_render) mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS; @@ -379,7 +387,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i); /* hsdes: 1809175790 */ - if (has_aux_ccs(xe)) + if (aux_ccs) i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i); dw[i++] = preparser_disable(false); diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h index d7e3e150a9a5..477dc7defd72 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops_types.h +++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h @@ -8,7 +8,7 @@ struct xe_sched_job; -#define MAX_JOB_SIZE_DW 58 +#define MAX_JOB_SIZE_DW 70 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4) /** -- 2.48.0