From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38E27CCD1A5 for ; Fri, 24 Oct 2025 10:08:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F17D810EA3E; Fri, 24 Oct 2025 10:08:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fFbz8KZy"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8070810EA33; Fri, 24 Oct 2025 10:08:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761300488; x=1792836488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tqjiqJUu6e8zqWSGYvXhbGWHMPwsHNlcc4LMYrcRwgI=; b=fFbz8KZyEet7InrZUIDLFxOBS7QSLf9T/HY/t89f46+CThOLaLHduXJX PJmeG2mGiDpcA/JH1S459OKYzXLPRcmaVvzVV3eRdYwIOnr/2EMApLjDo 1o22WrZZISWaW2JyAVCfee76wGeylhZ8CGInRXjfkbUkr/EpaLFwWdZb/ uHU9zmqCweqWqEuxJkMY8FIH9QlufiT/eqqmjcjEWoqSpUaJ6N3DHXwqN WTEoUpGDIfngpmUObBc68wc2alqjYVznWk+Kw1zt7tI6iyaCroVxxI0H/ aZ5Mq9sFThdC7WIdlhp5hKF+r64/l1bB8KEZs3OtCU0vYEFTiptfJ0zqw Q==; X-CSE-ConnectionGUID: meyX25ElTseoTsW/OFYaVA== X-CSE-MsgGUID: djoFxgxdTTioXUJMnxEE6g== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="67346841" X-IronPort-AV: E=Sophos;i="6.19,252,1754982000"; d="scan'208";a="67346841" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2025 03:08:08 -0700 X-CSE-ConnectionGUID: QL5WY/3ZT4yCfVRaZR6Bcg== X-CSE-MsgGUID: GsmJySJJSku4c+b/oKicDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,252,1754982000"; d="scan'208";a="208039295" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa002.fm.intel.com with ESMTP; 24 Oct 2025 03:08:05 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com, uma.shankar@intel.com, gustavo.sousa@intel.com, lucas.demarchi@intel.com, Suraj Kandpal Subject: [PATCH v2 17/26] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Date: Fri, 24 Oct 2025 15:37:03 +0530 Message-Id: <20251024100712.3776261-18-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024100712.3776261-1-suraj.kandpal@intel.com> References: <20251024100712.3776261-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Hook up the LT Phy enable and disable sequences using encoder-> enable/disable_clock and reusing the TBT enable disable sequence from cx0 PHY since it remains the same. Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 3 +++ drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++- drivers/gpu/drm/i915/display/intel_lt_phy.c | 21 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 +++ 5 files changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index a1c718f2fe02..bfaa21e8cb27 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -18,6 +18,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_hdmi.h" +#include "intel_lt_phy.h" #include "intel_panel.h" #include "intel_psr.h" #include "intel_snps_hdmi_pll.h" @@ -3151,8 +3152,8 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display, } } -static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -3336,7 +3337,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder) intel_cx0_get_pclk_pll_request(lane); } -static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) +void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index f0f0efa2d48b..a37827482a32 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -64,5 +64,8 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); void intel_cx0_pll_power_save_wa(struct intel_display *display); void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); +void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder); #endif /* __INTEL_CX0_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 870140340342..a4ea9f29fd85 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -72,6 +72,7 @@ #include "intel_hotplug.h" #include "intel_hti.h" #include "intel_lspcon.h" +#include "intel_lt_phy.h" #include "intel_mg_phy_regs.h" #include "intel_modeset_lock.h" #include "intel_panel.h" @@ -5231,7 +5232,11 @@ void intel_ddi_init(struct intel_display *display, encoder->cloneable = 0; encoder->pipe_mask = ~0; - if (DISPLAY_VER(display) >= 14) { + if (HAS_LT_PHY(display)) { + encoder->enable_clock = intel_xe3plpd_pll_enable; + encoder->disable_clock = intel_xe3plpd_pll_disable; + encoder->port_pll_type = intel_mtl_port_pll_type; + } else if (DISPLAY_VER(display) >= 14) { encoder->enable_clock = intel_mtl_pll_enable; encoder->disable_clock = intel_mtl_pll_disable; encoder->port_pll_type = intel_mtl_port_pll_type; diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index d86d44dec14f..2be48c3943dc 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1688,3 +1688,24 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder) intel_lt_phy_transaction_end(encoder, wakeref); } + +void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + if (intel_tc_port_in_tbt_alt_mode(dig_port)) + intel_mtl_tbt_pll_enable(encoder, crtc_state); + else + intel_lt_phy_pll_enable(encoder, crtc_state); +} + +void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + if (intel_tc_port_in_tbt_alt_mode(dig_port)) + intel_mtl_tbt_pll_disable(encoder); + else + intel_lt_phy_pll_disable(encoder); +} diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h index 499091e04e82..15d3d680871c 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h @@ -20,6 +20,9 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder); int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); +void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35) -- 2.34.1