From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64E86CCD1AB for ; Fri, 24 Oct 2025 10:07:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2CF7410EA1C; Fri, 24 Oct 2025 10:07:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OTRdfWy/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6225910EA1D; Fri, 24 Oct 2025 10:07:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761300451; x=1792836451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cSihDbDHcC2GMkhgUhmGN5jb5dbhRNCA1618P84mrgs=; b=OTRdfWy/vHrTenGPthNGeWeBQ61HCUJpjxS3k0cYqE0KBQuUjc7RjPg7 u8SogEABpNY9J98pzO3udnajO8dTfzY87wyLPxfZsgPVm3YC5ZELl5vGo kEVPs5EkpRd85evanLoRsBY/qdIandPTHBdZFDVnEBR4x/1UFjTXqO9DF jxo0v1li4INZt7gD4U9pX7FMCRV8w/oj1f/PKNY7b86RZLWXKilWs68E8 tAFGfZYFj1nMBwXLEC3DpCI3ifBlVkBE/gZ+gKE3mpuJgGTOj0AVAYN8k VPTldTKNoy83wGkdyieP2Tqn9JdUli0q99Cqp9VAlgt1z2qMg1l07FPgN Q==; X-CSE-ConnectionGUID: 29kmuv5yRIO+F0ylPbJ/Xg== X-CSE-MsgGUID: 6VqsVUkfTteMcP0pZdAEQw== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="81108491" X-IronPort-AV: E=Sophos;i="6.19,252,1754982000"; d="scan'208";a="81108491" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2025 03:07:30 -0700 X-CSE-ConnectionGUID: 1GEQugGWQVq4H04TLvjlbA== X-CSE-MsgGUID: qoWocmOKQJCHgorlf1XZPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,252,1754982000"; d="scan'208";a="208039149" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa002.fm.intel.com with ESMTP; 24 Oct 2025 03:07:27 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com, uma.shankar@intel.com, gustavo.sousa@intel.com, lucas.demarchi@intel.com, Suraj Kandpal Subject: [PATCH v2 04/26] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi Date: Fri, 24 Oct 2025 15:36:50 +0530 Message-Id: <20251024100712.3776261-5-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024100712.3776261-1-suraj.kandpal@intel.com> References: <20251024100712.3776261-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and make it non static. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 21 +++----------------- drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +++++++++++++ drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index c99e0885e737..6991707abdc7 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2590,20 +2590,6 @@ static bool is_dp2(u32 clock) return false; } -static bool is_hdmi_frl(u32 clock) -{ - switch (clock) { - case 300000: /* 3 Gbps */ - case 600000: /* 6 Gbps */ - case 800000: /* 8 Gbps */ - case 1000000: /* 10 Gbps */ - case 1200000: /* 12 Gbps */ - return true; - default: - return false; - } -} - static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) { struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); @@ -2617,7 +2603,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp) { if (dp && is_dp2(clock)) return 2; - else if (is_hdmi_frl(clock)) + else if (intel_hdmi_is_frl(clock)) return 1; else return 0; @@ -2706,11 +2692,10 @@ static void intel_c20_pll_program(struct intel_display *display, /* 5. For DP or 6. For HDMI */ serdes = 0; - if (is_dp) serdes = PHY_C20_IS_DP | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)); - else if (is_hdmi_frl(port_clock)) + else if (intel_hdmi_is_frl(port_clock)) serdes = PHY_C20_IS_HDMI_FRL; intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, @@ -2777,7 +2762,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, val |= XELPDP_FORWARD_CLOCK_UNGATE; - if (!is_dp && is_hdmi_frl(port_clock)) + if (!is_dp && intel_hdmi_is_frl(port_clock)) val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); else val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 4ab7e2e3bfd4..e81c3e5aa250 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -68,6 +68,20 @@ #include "intel_snps_phy.h" #include "intel_vrr.h" +bool intel_hdmi_is_frl(u32 clock) +{ + switch (clock) { + case 300000: /* 3 Gbps */ + case 600000: /* 6 Gbps */ + case 800000: /* 8 Gbps */ + case 1000000: /* 10 Gbps */ + case 1200000: /* 12 Gbps */ + return true; + default: + return false; + } +} + static void assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) { diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index dec2ad7dd8a2..be2fad57e4ad 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -60,6 +60,7 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, int src_max_slices, int src_max_slice_width, int hdmi_max_slices, int hdmi_throughput); int intel_hdmi_dsc_get_slice_height(int vactive); +bool intel_hdmi_is_frl(u32 clock); void hsw_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, -- 2.34.1