From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A2DBCCF9E0 for ; Fri, 24 Oct 2025 10:07:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2CD3610EA19; Fri, 24 Oct 2025 10:07:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Be9qKrnl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 33EA110EA1C; Fri, 24 Oct 2025 10:07:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761300453; x=1792836453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1rMwTkeSYipBTMtWhUw133Iu2z5Fa3aQ73620ZSfDdQ=; b=Be9qKrnltM68GMy2vYhNvgDT860Ax5gjx7KL2GmM0YVge4OBT6yc1ort sMC9yl1alz7SnEnu/NTynortvmJdo7vIbiQ1KFf0qkvx2Uf7Aidy9jlQ4 UysvPslOCYbxXBfbu0xV3Z+cqva9AjuntfnrsNEgWG/WcMV01pwhcB239 EGPIUSVqBLeHHyd3Aft37DQhPyJAtgkkUtnAHVhjmNqBFre2v/OpdBfam fQnvE8wAjXFQ+Dte3zHKwqcnJ24KodDbB8Ue3eLXc6J/WiH3cvOuvq/YY cWXRh+Xba4Ai7jIg9g60dshcxUa22xmibAplBhH1aOs3FjlE5uv1t7QWW Q==; X-CSE-ConnectionGUID: cfDJf/mLTSirziGRGjbOXA== X-CSE-MsgGUID: U0ZcArxrQ6OMU0RhmUFi2A== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="81108500" X-IronPort-AV: E=Sophos;i="6.19,252,1754982000"; d="scan'208";a="81108500" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2025 03:07:33 -0700 X-CSE-ConnectionGUID: ptj1Hjz2TXaWGDSBu21Wjg== X-CSE-MsgGUID: gX0dLjK4SmirN3v1E79bgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,252,1754982000"; d="scan'208";a="208039165" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.10]) by fmviesa002.fm.intel.com with ESMTP; 24 Oct 2025 03:07:30 -0700 From: Suraj Kandpal To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com, uma.shankar@intel.com, gustavo.sousa@intel.com, lucas.demarchi@intel.com, Suraj Kandpal Subject: [PATCH v2 05/26] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy Date: Fri, 24 Oct 2025 15:36:51 +0530 Message-Id: <20251024100712.3776261-6-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024100712.3776261-1-suraj.kandpal@intel.com> References: <20251024100712.3776261-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Program sequence from port clock ctl except for the SSC enablement part which will be taken care of later. Bspec: 74492 Signed-off-by: Suraj Kandpal --- V1 -> V2: Break patch into two (Arun) --- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 + drivers/gpu/drm/i915/display/intel_lt_phy.c | 37 ++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index c92026fe7b8f..b111a893b428 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); void intel_cx0_setup_powerdown(struct intel_encoder *encoder); +bool intel_cx0_is_hdmi_frl(u32 clock); int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); void intel_cx0_pll_power_save_wa(struct intel_display *display); void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index c65333cc9494..b6f71425cd19 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -11,6 +11,7 @@ #include "intel_de.h" #include "intel_display.h" #include "intel_display_types.h" +#include "intel_hdmi.h" #include "intel_lt_phy.h" #include "intel_lt_phy_regs.h" #include "intel_tc.h" @@ -108,13 +109,49 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder, intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0); } +static void +intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + bool lane_reversal) +{ + struct intel_display *display = to_intel_display(encoder); + u32 val = 0; + + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), + XELPDP_PORT_REVERSAL, + lane_reversal ? XELPDP_PORT_REVERSAL : 0); + + val |= XELPDP_FORWARD_CLOCK_UNGATE; + + /* + * We actually mean MACCLK here and not MAXPCLK when using LT Phy + * but since the register bits still remain the same we use + * the same definition + */ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && + intel_hdmi_is_frl(crtc_state->port_clock)) + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); + else + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); + + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), + XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | + XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA | + XELPDP_SSC_ENABLE_PLLB, val); +} + void intel_lt_phy_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + bool lane_reversal = dig_port->lane_reversal; + /* 1. Enable MacCLK at default 162 MHz frequency. */ intel_lt_phy_lane_reset(encoder, crtc_state->lane_count); /* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */ + intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal); + /* 3. Change owned PHY lanes power to Ready state. */ /* * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type, -- 2.34.1