[PATCH AUTOSEL 6.17] drm/xe/i2c: Enable bus mastering

[Sasha Levin <sashal@kernel.org>]

From: Raag Jadav <raag.jadav@intel.com>

[ Upstream commit fce99326c9cf5a0e57c4283a61c6b622ef5b0de8 ]

Enable bus mastering for I2C controller to support device initiated
in-band transactions.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Link: https://lore.kernel.org/r/20250908055320.2549722-1-raag.jadav@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

YES

Explanation

- What changed: In `xe_i2c_pm_resume()` the code now sets the PCI bus
  master enable bit for the Xe I2C controller when resuming from D3cold:
  - `drivers/gpu/drm/xe/xe_i2c.c:262` sets `PCI_COMMAND_MEMORY |
    PCI_COMMAND_MASTER` into the I2C controller’s pseudo PCI command
    register (`I2C_CONFIG_CMD`) instead of only `PCI_COMMAND_MEMORY`.
  - The target register is defined as the controller’s PCI Command
    aperture: `drivers/gpu/drm/xe/regs/xe_i2c_regs.h:17` (`#define
    I2C_CONFIG_CMD ... + PCI_COMMAND`), confirming this is the correct
    place to enable bus mastering.

- Why it matters: The commit message states the purpose clearly:
  enabling bus mastering is required “to support device initiated in-
  band transactions.” For DMA-capable controllers, PCI bus mastering
  must be enabled for the device to perform DMA. Without this bit set
  after D3cold, device-initiated I2C transactions that rely on DMA can
  fail or be unreliable. This is a functional bug for platforms using
  this path (e.g., Battlemage), not a feature add.

- Scope and containment:
  - Change is a single-line modification in one function, gated on
    `d3cold` and only executed when the controller is present
    (`xe_i2c_present()` guards the PM functions).
    - Presence check path: `drivers/gpu/drm/xe/xe_i2c.c:243` (suspend)
      and `drivers/gpu/drm/xe/xe_i2c.c:254` (resume) both early-return
      if the I2C endpoint isn’t valid.
  - The resume path is called from both probe and system resume:
    - Probe explicitly brings the controller up via
      `xe_i2c_pm_resume(xe, true);` so the bus master bit needs to be
      set there as well: `drivers/gpu/drm/xe/xe_i2c.c:318`.
    - System resume calls `xe_i2c_pm_resume(xe, xe->d3cold.allowed);`,
      so the bit is set only when returning from D3cold, which is when
      the bit would be lost: `drivers/gpu/drm/xe/xe_pm.c:204`.

- Risk and side effects:
  - Enabling `PCI_COMMAND_MASTER` is standard practice for DMA-capable
    devices and is required for correct operation of DMA paths. The
    change does not alter architecture or interfaces and is limited to
    the Xe I2C controller’s PM resume path after D3cold.
  - The write only happens if the controller is present and only on
    D3cold resume, minimizing exposure. There are no ABI or UAPI
    changes, and no wider subsystem impact.

- Stable backport criteria:
  - Fixes a real functional issue affecting users (device-initiated in-
    band I2C transactions fail without bus mastering).
  - Small, contained, and low risk (one line, single driver file, gated
    by presence and D3cold state).
  - No architectural changes or new features; this corrects an
    initialization oversight.
  - Touches DRM/xe I2C code only; no cross-subsystem churn.

Given the above, this is a clear, minimal bugfix that restores intended
functionality and is appropriate for stable backporting.

 drivers/gpu/drm/xe/xe_i2c.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
index bc7dc2099470c..983e8e08e4739 100644
--- a/drivers/gpu/drm/xe/xe_i2c.c
+++ b/drivers/gpu/drm/xe/xe_i2c.c
@@ -245,7 +245,7 @@ void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold)
 		return;
 
 	if (d3cold)
-		xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY);
+		xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 
 	xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0);
 	drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));
-- 
2.51.0