* [PATCH 1/2] drm/xe: Use SG_TILE_ADDR_RANGE instead of TILE_ADDR_RANGE
2025-11-07 18:23 [PATCH 0/2] drm/xe: Tile address change Lucas De Marchi
@ 2025-11-07 18:23 ` Lucas De Marchi
2025-11-07 18:23 ` [PATCH 2/2] drm/xe/vram: Move forcewake down to get_flat_ccs_offset() Lucas De Marchi
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Lucas De Marchi @ 2025-11-07 18:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, fei.yang, Matt Roper
From: Fei Yang <fei.yang@intel.com>
The TILE_ADDR_RANGE register is not available on all platforms going
forward as it was deprecated and is being replaced by equivalent
registers within SoC MMIO space. While that doesn't happen, the
SG_TILE_ADDR_RANGE (base 0x1083a0) is still valid for all platforms
supported by xe. Use that instead.
BSpec: 59353, 54991
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 -
drivers/gpu/drm/xe/regs/xe_regs.h | 2 ++
drivers/gpu/drm/xe/xe_vram.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 2088256ad3819..917a088c28f24 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -101,7 +101,6 @@
#define XE2_LMEM_CFG XE_REG(0x48b0)
-#define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4)
#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
#define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 1926b4044314e..ad93c57edd17c 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -40,6 +40,8 @@
#define STOLEN_RESERVED XE_REG(0x1082c0)
#define WOPCM_SIZE_MASK REG_GENMASK64(9, 7)
+#define SG_TILE_ADDR_RANGE(_idx) XE_REG(0x1083a0 + (_idx) * 4)
+
#define MTL_RP_STATE_CAP XE_REG(0x138000)
#define MTL_GT_RPA_FREQUENCY XE_REG(0x138008)
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index b62a96f8ef9eb..56924f6a44ff2 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -274,7 +274,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
*tile_offset = 0;
} else {
- reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt->info.id));
+ reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));
*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
}
--
2.51.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] drm/xe/vram: Move forcewake down to get_flat_ccs_offset()
2025-11-07 18:23 [PATCH 0/2] drm/xe: Tile address change Lucas De Marchi
2025-11-07 18:23 ` [PATCH 1/2] drm/xe: Use SG_TILE_ADDR_RANGE instead of TILE_ADDR_RANGE Lucas De Marchi
@ 2025-11-07 18:23 ` Lucas De Marchi
2025-11-08 0:06 ` Matt Roper
2025-11-07 21:29 ` ✓ CI.KUnit: success for drm/xe: Tile address change Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2025-11-07 18:23 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, fei.yang, Matt Roper
With SG_TILE_ADDR_RANGE use, the only thing requiring GT forcewake while
probing for vram size is the get_flat_ccs_offset(). Move the forcewake
down where it's needed.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_vram.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 56924f6a44ff2..0e10da790cc5d 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -183,12 +183,17 @@ static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *
return 0;
}
-static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
+static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
{
struct xe_device *xe = gt_to_xe(gt);
+ unsigned int fw_ref;
u64 offset;
u32 reg;
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+ if (!fw_ref)
+ return -ETIMEDOUT;
+
if (GRAPHICS_VER(xe) >= 20) {
u64 ccs_size = tile_size / 512;
u64 offset_hi, offset_lo;
@@ -218,7 +223,10 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
}
- return offset;
+ xe_force_wake_put(gt_to_fw(gt), fw_ref);
+ *poffset = offset;
+
+ return 0;
}
/*
@@ -245,7 +253,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
{
struct xe_device *xe = tile_to_xe(tile);
struct xe_gt *gt = tile->primary_gt;
- unsigned int fw_ref;
u64 offset;
u32 reg;
@@ -265,10 +272,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
return 0;
}
- fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
- if (!fw_ref)
- return -ETIMEDOUT;
-
/* actual size */
if (unlikely(xe->info.platform == XE_DG1)) {
*tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
@@ -281,7 +284,10 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
/* minus device usage */
if (xe->info.has_flat_ccs) {
- offset = get_flat_ccs_offset(gt, *tile_size);
+ int ret = get_flat_ccs_offset(gt, *tile_size, &offset);
+
+ if (ret)
+ return ret;
} else {
offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
}
@@ -289,8 +295,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
/* remove the tile offset so we have just the available size */
*vram_size = offset - *tile_offset;
- xe_force_wake_put(gt_to_fw(gt), fw_ref);
-
return 0;
}
--
2.51.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] drm/xe/vram: Move forcewake down to get_flat_ccs_offset()
2025-11-07 18:23 ` [PATCH 2/2] drm/xe/vram: Move forcewake down to get_flat_ccs_offset() Lucas De Marchi
@ 2025-11-08 0:06 ` Matt Roper
0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2025-11-08 0:06 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe, fei.yang
On Fri, Nov 07, 2025 at 10:23:45AM -0800, Lucas De Marchi wrote:
> With SG_TILE_ADDR_RANGE use, the only thing requiring GT forcewake while
> probing for vram size is the get_flat_ccs_offset(). Move the forcewake
> down where it's needed.
>
> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
While reviewing this, I noticed that the xe_assert_msg() we have in
get_flat_ccs_offset probably should be a regular warning/error rather
than an assert since asserts are only checked in debug builds and should
be used for "we know this should be absolutely impossible based on
software logic" rather than "we hope the hardware/firmware is giving us
sensible values." But we can change that later.
Matt
> ---
> drivers/gpu/drm/xe/xe_vram.c | 24 ++++++++++++++----------
> 1 file changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 56924f6a44ff2..0e10da790cc5d 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -183,12 +183,17 @@ static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *
> return 0;
> }
>
> -static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> +static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
> {
> struct xe_device *xe = gt_to_xe(gt);
> + unsigned int fw_ref;
> u64 offset;
> u32 reg;
>
> + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> + if (!fw_ref)
> + return -ETIMEDOUT;
> +
> if (GRAPHICS_VER(xe) >= 20) {
> u64 ccs_size = tile_size / 512;
> u64 offset_hi, offset_lo;
> @@ -218,7 +223,10 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
> }
>
> - return offset;
> + xe_force_wake_put(gt_to_fw(gt), fw_ref);
> + *poffset = offset;
> +
> + return 0;
> }
>
> /*
> @@ -245,7 +253,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> {
> struct xe_device *xe = tile_to_xe(tile);
> struct xe_gt *gt = tile->primary_gt;
> - unsigned int fw_ref;
> u64 offset;
> u32 reg;
>
> @@ -265,10 +272,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> return 0;
> }
>
> - fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> - if (!fw_ref)
> - return -ETIMEDOUT;
> -
> /* actual size */
> if (unlikely(xe->info.platform == XE_DG1)) {
> *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), LMEM_BAR);
> @@ -281,7 +284,10 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
>
> /* minus device usage */
> if (xe->info.has_flat_ccs) {
> - offset = get_flat_ccs_offset(gt, *tile_size);
> + int ret = get_flat_ccs_offset(gt, *tile_size, &offset);
> +
> + if (ret)
> + return ret;
> } else {
> offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
> }
> @@ -289,8 +295,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> /* remove the tile offset so we have just the available size */
> *vram_size = offset - *tile_offset;
>
> - xe_force_wake_put(gt_to_fw(gt), fw_ref);
> -
> return 0;
> }
>
>
> --
> 2.51.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ CI.KUnit: success for drm/xe: Tile address change
2025-11-07 18:23 [PATCH 0/2] drm/xe: Tile address change Lucas De Marchi
2025-11-07 18:23 ` [PATCH 1/2] drm/xe: Use SG_TILE_ADDR_RANGE instead of TILE_ADDR_RANGE Lucas De Marchi
2025-11-07 18:23 ` [PATCH 2/2] drm/xe/vram: Move forcewake down to get_flat_ccs_offset() Lucas De Marchi
@ 2025-11-07 21:29 ` Patchwork
2025-11-07 22:29 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-11-07 21:29 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Tile address change
URL : https://patchwork.freedesktop.org/series/157254/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:27:42] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:27:46] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:28:24] Starting KUnit Kernel (1/1)...
[21:28:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:28:24] ================== guc_buf (11 subtests) ===================
[21:28:24] [PASSED] test_smallest
[21:28:24] [PASSED] test_largest
[21:28:24] [PASSED] test_granular
[21:28:24] [PASSED] test_unique
[21:28:24] [PASSED] test_overlap
[21:28:24] [PASSED] test_reusable
[21:28:24] [PASSED] test_too_big
[21:28:24] [PASSED] test_flush
[21:28:24] [PASSED] test_lookup
[21:28:24] [PASSED] test_data
[21:28:24] [PASSED] test_class
[21:28:24] ===================== [PASSED] guc_buf =====================
[21:28:24] =================== guc_dbm (7 subtests) ===================
[21:28:24] [PASSED] test_empty
[21:28:24] [PASSED] test_default
[21:28:24] ======================== test_size ========================
[21:28:24] [PASSED] 4
[21:28:24] [PASSED] 8
[21:28:24] [PASSED] 32
[21:28:24] [PASSED] 256
[21:28:24] ==================== [PASSED] test_size ====================
[21:28:24] ======================= test_reuse ========================
[21:28:24] [PASSED] 4
[21:28:24] [PASSED] 8
[21:28:24] [PASSED] 32
[21:28:24] [PASSED] 256
[21:28:24] =================== [PASSED] test_reuse ====================
[21:28:24] =================== test_range_overlap ====================
[21:28:24] [PASSED] 4
[21:28:24] [PASSED] 8
[21:28:24] [PASSED] 32
[21:28:24] [PASSED] 256
[21:28:24] =============== [PASSED] test_range_overlap ================
[21:28:24] =================== test_range_compact ====================
[21:28:24] [PASSED] 4
[21:28:24] [PASSED] 8
[21:28:24] [PASSED] 32
[21:28:24] [PASSED] 256
[21:28:24] =============== [PASSED] test_range_compact ================
[21:28:24] ==================== test_range_spare =====================
[21:28:24] [PASSED] 4
[21:28:24] [PASSED] 8
[21:28:24] [PASSED] 32
[21:28:24] [PASSED] 256
[21:28:24] ================ [PASSED] test_range_spare =================
[21:28:24] ===================== [PASSED] guc_dbm =====================
[21:28:24] =================== guc_idm (6 subtests) ===================
[21:28:24] [PASSED] bad_init
[21:28:24] [PASSED] no_init
[21:28:24] [PASSED] init_fini
[21:28:24] [PASSED] check_used
[21:28:24] [PASSED] check_quota
[21:28:24] [PASSED] check_all
[21:28:24] ===================== [PASSED] guc_idm =====================
[21:28:24] ================== no_relay (3 subtests) ===================
[21:28:24] [PASSED] xe_drops_guc2pf_if_not_ready
[21:28:24] [PASSED] xe_drops_guc2vf_if_not_ready
[21:28:24] [PASSED] xe_rejects_send_if_not_ready
[21:28:24] ==================== [PASSED] no_relay =====================
[21:28:24] ================== pf_relay (14 subtests) ==================
[21:28:24] [PASSED] pf_rejects_guc2pf_too_short
[21:28:24] [PASSED] pf_rejects_guc2pf_too_long
[21:28:24] [PASSED] pf_rejects_guc2pf_no_payload
[21:28:24] [PASSED] pf_fails_no_payload
[21:28:24] [PASSED] pf_fails_bad_origin
[21:28:24] [PASSED] pf_fails_bad_type
[21:28:24] [PASSED] pf_txn_reports_error
[21:28:24] [PASSED] pf_txn_sends_pf2guc
[21:28:24] [PASSED] pf_sends_pf2guc
[21:28:24] [SKIPPED] pf_loopback_nop
[21:28:24] [SKIPPED] pf_loopback_echo
[21:28:24] [SKIPPED] pf_loopback_fail
[21:28:24] [SKIPPED] pf_loopback_busy
[21:28:24] [SKIPPED] pf_loopback_retry
[21:28:24] ==================== [PASSED] pf_relay =====================
[21:28:24] ================== vf_relay (3 subtests) ===================
[21:28:24] [PASSED] vf_rejects_guc2vf_too_short
[21:28:24] [PASSED] vf_rejects_guc2vf_too_long
[21:28:24] [PASSED] vf_rejects_guc2vf_no_payload
[21:28:24] ==================== [PASSED] vf_relay =====================
[21:28:24] ================ pf_gt_config (4 subtests) =================
[21:28:24] [PASSED] fair_contexts_1vf
[21:28:24] [PASSED] fair_doorbells_1vf
[21:28:24] ====================== fair_contexts ======================
[21:28:24] [PASSED] 1 VF
[21:28:24] [PASSED] 2 VFs
[21:28:24] [PASSED] 3 VFs
[21:28:24] [PASSED] 4 VFs
[21:28:24] [PASSED] 5 VFs
[21:28:24] [PASSED] 6 VFs
[21:28:24] [PASSED] 7 VFs
[21:28:24] [PASSED] 8 VFs
[21:28:24] [PASSED] 9 VFs
[21:28:24] [PASSED] 10 VFs
[21:28:24] [PASSED] 11 VFs
[21:28:24] [PASSED] 12 VFs
[21:28:24] [PASSED] 13 VFs
[21:28:24] [PASSED] 14 VFs
[21:28:24] [PASSED] 15 VFs
[21:28:24] [PASSED] 16 VFs
[21:28:24] [PASSED] 17 VFs
[21:28:24] [PASSED] 18 VFs
[21:28:24] [PASSED] 19 VFs
[21:28:24] [PASSED] 20 VFs
[21:28:24] [PASSED] 21 VFs
[21:28:24] [PASSED] 22 VFs
[21:28:24] [PASSED] 23 VFs
[21:28:24] [PASSED] 24 VFs
[21:28:24] [PASSED] 25 VFs
[21:28:24] [PASSED] 26 VFs
[21:28:24] [PASSED] 27 VFs
[21:28:24] [PASSED] 28 VFs
[21:28:24] [PASSED] 29 VFs
[21:28:24] [PASSED] 30 VFs
[21:28:24] [PASSED] 31 VFs
[21:28:24] [PASSED] 32 VFs
[21:28:24] [PASSED] 33 VFs
[21:28:24] [PASSED] 34 VFs
[21:28:24] [PASSED] 35 VFs
[21:28:24] [PASSED] 36 VFs
[21:28:24] [PASSED] 37 VFs
[21:28:24] [PASSED] 38 VFs
[21:28:24] [PASSED] 39 VFs
[21:28:24] [PASSED] 40 VFs
[21:28:24] [PASSED] 41 VFs
[21:28:24] [PASSED] 42 VFs
[21:28:24] [PASSED] 43 VFs
[21:28:24] [PASSED] 44 VFs
[21:28:24] [PASSED] 45 VFs
[21:28:24] [PASSED] 46 VFs
[21:28:24] [PASSED] 47 VFs
[21:28:24] [PASSED] 48 VFs
[21:28:24] [PASSED] 49 VFs
[21:28:24] [PASSED] 50 VFs
[21:28:24] [PASSED] 51 VFs
[21:28:24] [PASSED] 52 VFs
[21:28:24] [PASSED] 53 VFs
[21:28:24] [PASSED] 54 VFs
[21:28:24] [PASSED] 55 VFs
[21:28:24] [PASSED] 56 VFs
[21:28:24] [PASSED] 57 VFs
[21:28:24] [PASSED] 58 VFs
[21:28:24] [PASSED] 59 VFs
[21:28:24] [PASSED] 60 VFs
[21:28:24] [PASSED] 61 VFs
[21:28:24] [PASSED] 62 VFs
[21:28:24] [PASSED] 63 VFs
[21:28:24] ================== [PASSED] fair_contexts ==================
[21:28:24] ===================== fair_doorbells ======================
[21:28:24] [PASSED] 1 VF
[21:28:24] [PASSED] 2 VFs
[21:28:24] [PASSED] 3 VFs
[21:28:24] [PASSED] 4 VFs
[21:28:24] [PASSED] 5 VFs
[21:28:24] [PASSED] 6 VFs
[21:28:24] [PASSED] 7 VFs
[21:28:24] [PASSED] 8 VFs
[21:28:24] [PASSED] 9 VFs
[21:28:24] [PASSED] 10 VFs
[21:28:24] [PASSED] 11 VFs
[21:28:24] [PASSED] 12 VFs
[21:28:24] [PASSED] 13 VFs
[21:28:24] [PASSED] 14 VFs
[21:28:24] [PASSED] 15 VFs
[21:28:24] [PASSED] 16 VFs
[21:28:24] [PASSED] 17 VFs
[21:28:24] [PASSED] 18 VFs
[21:28:24] [PASSED] 19 VFs
[21:28:24] [PASSED] 20 VFs
[21:28:24] [PASSED] 21 VFs
[21:28:24] [PASSED] 22 VFs
[21:28:24] [PASSED] 23 VFs
[21:28:24] [PASSED] 24 VFs
[21:28:24] [PASSED] 25 VFs
[21:28:24] [PASSED] 26 VFs
[21:28:24] [PASSED] 27 VFs
[21:28:24] [PASSED] 28 VFs
[21:28:24] [PASSED] 29 VFs
[21:28:24] [PASSED] 30 VFs
[21:28:24] [PASSED] 31 VFs
[21:28:24] [PASSED] 32 VFs
[21:28:24] [PASSED] 33 VFs
[21:28:24] [PASSED] 34 VFs
[21:28:24] [PASSED] 35 VFs
[21:28:24] [PASSED] 36 VFs
[21:28:24] [PASSED] 37 VFs
[21:28:24] [PASSED] 38 VFs
[21:28:24] [PASSED] 39 VFs
[21:28:24] [PASSED] 40 VFs
[21:28:24] [PASSED] 41 VFs
[21:28:24] [PASSED] 42 VFs
[21:28:24] [PASSED] 43 VFs
[21:28:24] [PASSED] 44 VFs
[21:28:24] [PASSED] 45 VFs
[21:28:24] [PASSED] 46 VFs
[21:28:24] [PASSED] 47 VFs
[21:28:24] [PASSED] 48 VFs
[21:28:24] [PASSED] 49 VFs
[21:28:24] [PASSED] 50 VFs
[21:28:24] [PASSED] 51 VFs
[21:28:24] [PASSED] 52 VFs
[21:28:24] [PASSED] 53 VFs
[21:28:24] [PASSED] 54 VFs
[21:28:24] [PASSED] 55 VFs
[21:28:24] [PASSED] 56 VFs
[21:28:24] [PASSED] 57 VFs
[21:28:24] [PASSED] 58 VFs
[21:28:24] [PASSED] 59 VFs
[21:28:24] [PASSED] 60 VFs
[21:28:24] [PASSED] 61 VFs
[21:28:24] [PASSED] 62 VFs
[21:28:24] [PASSED] 63 VFs
[21:28:24] ================= [PASSED] fair_doorbells ==================
[21:28:24] ================== [PASSED] pf_gt_config ===================
[21:28:24] ===================== lmtt (1 subtest) =====================
[21:28:24] ======================== test_ops =========================
[21:28:24] [PASSED] 2-level
[21:28:24] [PASSED] multi-level
[21:28:24] ==================== [PASSED] test_ops =====================
[21:28:24] ====================== [PASSED] lmtt =======================
[21:28:24] ================= pf_service (11 subtests) =================
[21:28:24] [PASSED] pf_negotiate_any
[21:28:24] [PASSED] pf_negotiate_base_match
[21:28:24] [PASSED] pf_negotiate_base_newer
[21:28:24] [PASSED] pf_negotiate_base_next
[21:28:24] [SKIPPED] pf_negotiate_base_older
[21:28:24] [PASSED] pf_negotiate_base_prev
[21:28:24] [PASSED] pf_negotiate_latest_match
[21:28:24] [PASSED] pf_negotiate_latest_newer
[21:28:24] [PASSED] pf_negotiate_latest_next
[21:28:24] [SKIPPED] pf_negotiate_latest_older
[21:28:24] [SKIPPED] pf_negotiate_latest_prev
[21:28:24] =================== [PASSED] pf_service ====================
[21:28:24] ================= xe_guc_g2g (2 subtests) ==================
[21:28:24] ============== xe_live_guc_g2g_kunit_default ==============
[21:28:24] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:28:24] ============== xe_live_guc_g2g_kunit_allmem ===============
[21:28:24] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:28:24] =================== [SKIPPED] xe_guc_g2g ===================
[21:28:24] =================== xe_mocs (2 subtests) ===================
[21:28:24] ================ xe_live_mocs_kernel_kunit ================
[21:28:24] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:28:24] ================ xe_live_mocs_reset_kunit =================
[21:28:24] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:28:24] ==================== [SKIPPED] xe_mocs =====================
[21:28:24] ================= xe_migrate (2 subtests) ==================
[21:28:24] ================= xe_migrate_sanity_kunit =================
[21:28:24] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:28:24] ================== xe_validate_ccs_kunit ==================
[21:28:24] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:28:24] =================== [SKIPPED] xe_migrate ===================
[21:28:24] ================== xe_dma_buf (1 subtest) ==================
[21:28:24] ==================== xe_dma_buf_kunit =====================
[21:28:24] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:28:24] =================== [SKIPPED] xe_dma_buf ===================
[21:28:24] ================= xe_bo_shrink (1 subtest) =================
[21:28:24] =================== xe_bo_shrink_kunit ====================
[21:28:24] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:28:24] ================== [SKIPPED] xe_bo_shrink ==================
[21:28:24] ==================== xe_bo (2 subtests) ====================
[21:28:24] ================== xe_ccs_migrate_kunit ===================
[21:28:24] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:28:24] ==================== xe_bo_evict_kunit ====================
[21:28:24] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:28:24] ===================== [SKIPPED] xe_bo ======================
[21:28:24] ==================== args (11 subtests) ====================
[21:28:24] [PASSED] count_args_test
[21:28:24] [PASSED] call_args_example
[21:28:24] [PASSED] call_args_test
[21:28:24] [PASSED] drop_first_arg_example
[21:28:24] [PASSED] drop_first_arg_test
[21:28:24] [PASSED] first_arg_example
[21:28:24] [PASSED] first_arg_test
[21:28:24] [PASSED] last_arg_example
[21:28:24] [PASSED] last_arg_test
[21:28:24] [PASSED] pick_arg_example
[21:28:24] [PASSED] sep_comma_example
[21:28:24] ====================== [PASSED] args =======================
[21:28:24] =================== xe_pci (3 subtests) ====================
[21:28:24] ==================== check_graphics_ip ====================
[21:28:24] [PASSED] 12.00 Xe_LP
[21:28:24] [PASSED] 12.10 Xe_LP+
[21:28:24] [PASSED] 12.55 Xe_HPG
[21:28:24] [PASSED] 12.60 Xe_HPC
[21:28:24] [PASSED] 12.70 Xe_LPG
[21:28:24] [PASSED] 12.71 Xe_LPG
[21:28:24] [PASSED] 12.74 Xe_LPG+
[21:28:24] [PASSED] 20.01 Xe2_HPG
[21:28:24] [PASSED] 20.02 Xe2_HPG
[21:28:24] [PASSED] 20.04 Xe2_LPG
[21:28:24] [PASSED] 30.00 Xe3_LPG
[21:28:24] [PASSED] 30.01 Xe3_LPG
[21:28:24] [PASSED] 30.03 Xe3_LPG
[21:28:24] [PASSED] 30.04 Xe3_LPG
[21:28:24] [PASSED] 30.05 Xe3_LPG
[21:28:24] [PASSED] 35.11 Xe3p_XPC
[21:28:24] ================ [PASSED] check_graphics_ip ================
[21:28:24] ===================== check_media_ip ======================
[21:28:24] [PASSED] 12.00 Xe_M
[21:28:24] [PASSED] 12.55 Xe_HPM
[21:28:24] [PASSED] 13.00 Xe_LPM+
[21:28:24] [PASSED] 13.01 Xe2_HPM
[21:28:24] [PASSED] 20.00 Xe2_LPM
[21:28:24] [PASSED] 30.00 Xe3_LPM
[21:28:24] [PASSED] 30.02 Xe3_LPM
[21:28:24] [PASSED] 35.00 Xe3p_LPM
[21:28:24] [PASSED] 35.03 Xe3p_HPM
[21:28:24] ================= [PASSED] check_media_ip ==================
[21:28:24] =================== check_platform_desc ===================
[21:28:24] [PASSED] 0x9A60 (TIGERLAKE)
[21:28:24] [PASSED] 0x9A68 (TIGERLAKE)
[21:28:24] [PASSED] 0x9A70 (TIGERLAKE)
[21:28:24] [PASSED] 0x9A40 (TIGERLAKE)
[21:28:24] [PASSED] 0x9A49 (TIGERLAKE)
[21:28:24] [PASSED] 0x9A59 (TIGERLAKE)
[21:28:24] [PASSED] 0x9A78 (TIGERLAKE)
[21:28:24] [PASSED] 0x9AC0 (TIGERLAKE)
[21:28:24] [PASSED] 0x9AC9 (TIGERLAKE)
[21:28:24] [PASSED] 0x9AD9 (TIGERLAKE)
[21:28:24] [PASSED] 0x9AF8 (TIGERLAKE)
[21:28:24] [PASSED] 0x4C80 (ROCKETLAKE)
[21:28:24] [PASSED] 0x4C8A (ROCKETLAKE)
[21:28:24] [PASSED] 0x4C8B (ROCKETLAKE)
[21:28:24] [PASSED] 0x4C8C (ROCKETLAKE)
[21:28:24] [PASSED] 0x4C90 (ROCKETLAKE)
[21:28:24] [PASSED] 0x4C9A (ROCKETLAKE)
[21:28:24] [PASSED] 0x4680 (ALDERLAKE_S)
[21:28:24] [PASSED] 0x4682 (ALDERLAKE_S)
[21:28:24] [PASSED] 0x4688 (ALDERLAKE_S)
[21:28:24] [PASSED] 0x468A (ALDERLAKE_S)
[21:28:24] [PASSED] 0x468B (ALDERLAKE_S)
[21:28:24] [PASSED] 0x4690 (ALDERLAKE_S)
[21:28:24] [PASSED] 0x4692 (ALDERLAKE_S)
[21:28:24] [PASSED] 0x4693 (ALDERLAKE_S)
[21:28:24] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46AA (ALDERLAKE_P)
[21:28:24] [PASSED] 0x462A (ALDERLAKE_P)
[21:28:24] [PASSED] 0x4626 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x4628 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:28:24] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:28:24] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:28:24] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:28:24] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:28:24] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:28:24] [PASSED] 0xA721 (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA720 (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:28:24] [PASSED] 0xA780 (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA781 (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA782 (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA783 (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA788 (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA789 (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA78A (ALDERLAKE_S)
[21:28:24] [PASSED] 0xA78B (ALDERLAKE_S)
[21:28:24] [PASSED] 0x4905 (DG1)
[21:28:24] [PASSED] 0x4906 (DG1)
[21:28:24] [PASSED] 0x4907 (DG1)
[21:28:24] [PASSED] 0x4908 (DG1)
[21:28:24] [PASSED] 0x4909 (DG1)
[21:28:24] [PASSED] 0x56C0 (DG2)
[21:28:24] [PASSED] 0x56C2 (DG2)
[21:28:24] [PASSED] 0x56C1 (DG2)
[21:28:24] [PASSED] 0x7D51 (METEORLAKE)
[21:28:24] [PASSED] 0x7DD1 (METEORLAKE)
[21:28:24] [PASSED] 0x7D41 (METEORLAKE)
[21:28:24] [PASSED] 0x7D67 (METEORLAKE)
[21:28:24] [PASSED] 0xB640 (METEORLAKE)
[21:28:24] [PASSED] 0x56A0 (DG2)
[21:28:24] [PASSED] 0x56A1 (DG2)
[21:28:24] [PASSED] 0x56A2 (DG2)
[21:28:24] [PASSED] 0x56BE (DG2)
[21:28:24] [PASSED] 0x56BF (DG2)
[21:28:24] [PASSED] 0x5690 (DG2)
stty: 'standard input': Inappropriate ioctl for device
[21:28:24] [PASSED] 0x5691 (DG2)
[21:28:24] [PASSED] 0x5692 (DG2)
[21:28:24] [PASSED] 0x56A5 (DG2)
[21:28:24] [PASSED] 0x56A6 (DG2)
[21:28:24] [PASSED] 0x56B0 (DG2)
[21:28:24] [PASSED] 0x56B1 (DG2)
[21:28:24] [PASSED] 0x56BA (DG2)
[21:28:24] [PASSED] 0x56BB (DG2)
[21:28:24] [PASSED] 0x56BC (DG2)
[21:28:24] [PASSED] 0x56BD (DG2)
[21:28:24] [PASSED] 0x5693 (DG2)
[21:28:24] [PASSED] 0x5694 (DG2)
[21:28:24] [PASSED] 0x5695 (DG2)
[21:28:24] [PASSED] 0x56A3 (DG2)
[21:28:24] [PASSED] 0x56A4 (DG2)
[21:28:24] [PASSED] 0x56B2 (DG2)
[21:28:24] [PASSED] 0x56B3 (DG2)
[21:28:24] [PASSED] 0x5696 (DG2)
[21:28:24] [PASSED] 0x5697 (DG2)
[21:28:24] [PASSED] 0xB69 (PVC)
[21:28:24] [PASSED] 0xB6E (PVC)
[21:28:24] [PASSED] 0xBD4 (PVC)
[21:28:24] [PASSED] 0xBD5 (PVC)
[21:28:24] [PASSED] 0xBD6 (PVC)
[21:28:24] [PASSED] 0xBD7 (PVC)
[21:28:24] [PASSED] 0xBD8 (PVC)
[21:28:24] [PASSED] 0xBD9 (PVC)
[21:28:24] [PASSED] 0xBDA (PVC)
[21:28:24] [PASSED] 0xBDB (PVC)
[21:28:24] [PASSED] 0xBE0 (PVC)
[21:28:24] [PASSED] 0xBE1 (PVC)
[21:28:24] [PASSED] 0xBE5 (PVC)
[21:28:24] [PASSED] 0x7D40 (METEORLAKE)
[21:28:24] [PASSED] 0x7D45 (METEORLAKE)
[21:28:24] [PASSED] 0x7D55 (METEORLAKE)
[21:28:24] [PASSED] 0x7D60 (METEORLAKE)
[21:28:24] [PASSED] 0x7DD5 (METEORLAKE)
[21:28:24] [PASSED] 0x6420 (LUNARLAKE)
[21:28:24] [PASSED] 0x64A0 (LUNARLAKE)
[21:28:24] [PASSED] 0x64B0 (LUNARLAKE)
[21:28:24] [PASSED] 0xE202 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE209 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE20B (BATTLEMAGE)
[21:28:24] [PASSED] 0xE20C (BATTLEMAGE)
[21:28:24] [PASSED] 0xE20D (BATTLEMAGE)
[21:28:24] [PASSED] 0xE210 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE211 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE212 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE216 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE220 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE221 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE222 (BATTLEMAGE)
[21:28:24] [PASSED] 0xE223 (BATTLEMAGE)
[21:28:24] [PASSED] 0xB080 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB081 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB082 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB083 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB084 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB085 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB086 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB087 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB08F (PANTHERLAKE)
[21:28:24] [PASSED] 0xB090 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:28:24] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:28:24] [PASSED] 0xD740 (NOVALAKE_S)
[21:28:24] [PASSED] 0xD741 (NOVALAKE_S)
[21:28:24] [PASSED] 0xD742 (NOVALAKE_S)
[21:28:24] [PASSED] 0xD743 (NOVALAKE_S)
[21:28:24] [PASSED] 0xD744 (NOVALAKE_S)
[21:28:24] [PASSED] 0xD745 (NOVALAKE_S)
[21:28:24] [PASSED] 0x674C (CRESCENTISLAND)
[21:28:24] [PASSED] 0xFD80 (PANTHERLAKE)
[21:28:24] [PASSED] 0xFD81 (PANTHERLAKE)
[21:28:24] =============== [PASSED] check_platform_desc ===============
[21:28:24] ===================== [PASSED] xe_pci ======================
[21:28:24] =================== xe_rtp (2 subtests) ====================
[21:28:24] =============== xe_rtp_process_to_sr_tests ================
[21:28:24] [PASSED] coalesce-same-reg
[21:28:24] [PASSED] no-match-no-add
[21:28:24] [PASSED] match-or
[21:28:24] [PASSED] match-or-xfail
[21:28:24] [PASSED] no-match-no-add-multiple-rules
[21:28:24] [PASSED] two-regs-two-entries
[21:28:24] [PASSED] clr-one-set-other
[21:28:24] [PASSED] set-field
[21:28:24] [PASSED] conflict-duplicate
[21:28:24] [PASSED] conflict-not-disjoint
[21:28:24] [PASSED] conflict-reg-type
[21:28:24] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:28:24] ================== xe_rtp_process_tests ===================
[21:28:24] [PASSED] active1
[21:28:24] [PASSED] active2
[21:28:24] [PASSED] active-inactive
[21:28:24] [PASSED] inactive-active
[21:28:24] [PASSED] inactive-1st_or_active-inactive
[21:28:24] [PASSED] inactive-2nd_or_active-inactive
[21:28:24] [PASSED] inactive-last_or_active-inactive
[21:28:24] [PASSED] inactive-no_or_active-inactive
[21:28:24] ============== [PASSED] xe_rtp_process_tests ===============
[21:28:24] ===================== [PASSED] xe_rtp ======================
[21:28:24] ==================== xe_wa (1 subtest) =====================
[21:28:24] ======================== xe_wa_gt =========================
[21:28:24] [PASSED] TIGERLAKE B0
[21:28:24] [PASSED] DG1 A0
[21:28:24] [PASSED] DG1 B0
[21:28:24] [PASSED] ALDERLAKE_S A0
[21:28:24] [PASSED] ALDERLAKE_S B0
[21:28:24] [PASSED] ALDERLAKE_S C0
[21:28:24] [PASSED] ALDERLAKE_S D0
[21:28:24] [PASSED] ALDERLAKE_P A0
[21:28:24] [PASSED] ALDERLAKE_P B0
[21:28:24] [PASSED] ALDERLAKE_P C0
[21:28:24] [PASSED] ALDERLAKE_S RPLS D0
[21:28:24] [PASSED] ALDERLAKE_P RPLU E0
[21:28:24] [PASSED] DG2 G10 C0
[21:28:24] [PASSED] DG2 G11 B1
[21:28:24] [PASSED] DG2 G12 A1
[21:28:24] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:28:24] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:28:24] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:28:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:28:24] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:28:24] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:28:24] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:28:24] ==================== [PASSED] xe_wa_gt =====================
[21:28:24] ====================== [PASSED] xe_wa ======================
[21:28:24] ============================================================
[21:28:24] Testing complete. Ran 446 tests: passed: 428, skipped: 18
[21:28:24] Elapsed time: 42.389s total, 4.291s configuring, 37.631s building, 0.425s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:28:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:28:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:28:56] Starting KUnit Kernel (1/1)...
[21:28:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:28:56] ============ drm_test_pick_cmdline (2 subtests) ============
[21:28:56] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:28:56] =============== drm_test_pick_cmdline_named ===============
[21:28:56] [PASSED] NTSC
[21:28:56] [PASSED] NTSC-J
[21:28:56] [PASSED] PAL
[21:28:56] [PASSED] PAL-M
[21:28:56] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:28:56] ============== [PASSED] drm_test_pick_cmdline ==============
[21:28:56] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:28:56] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:28:56] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:28:56] =========== drm_validate_clone_mode (2 subtests) ===========
[21:28:56] ============== drm_test_check_in_clone_mode ===============
[21:28:56] [PASSED] in_clone_mode
[21:28:56] [PASSED] not_in_clone_mode
[21:28:56] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:28:56] =============== drm_test_check_valid_clones ===============
[21:28:56] [PASSED] not_in_clone_mode
[21:28:56] [PASSED] valid_clone
[21:28:56] [PASSED] invalid_clone
[21:28:56] =========== [PASSED] drm_test_check_valid_clones ===========
[21:28:56] ============= [PASSED] drm_validate_clone_mode =============
[21:28:56] ============= drm_validate_modeset (1 subtest) =============
[21:28:56] [PASSED] drm_test_check_connector_changed_modeset
[21:28:56] ============== [PASSED] drm_validate_modeset ===============
[21:28:56] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:28:56] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:28:56] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:28:56] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:28:56] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:28:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:28:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:28:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:28:56] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:28:56] ============== drm_bridge_alloc (2 subtests) ===============
[21:28:56] [PASSED] drm_test_drm_bridge_alloc_basic
[21:28:56] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:28:56] ================ [PASSED] drm_bridge_alloc =================
[21:28:56] ================== drm_buddy (8 subtests) ==================
[21:28:56] [PASSED] drm_test_buddy_alloc_limit
[21:28:56] [PASSED] drm_test_buddy_alloc_optimistic
[21:28:56] [PASSED] drm_test_buddy_alloc_pessimistic
[21:28:56] [PASSED] drm_test_buddy_alloc_pathological
[21:28:56] [PASSED] drm_test_buddy_alloc_contiguous
[21:28:56] [PASSED] drm_test_buddy_alloc_clear
[21:28:56] [PASSED] drm_test_buddy_alloc_range_bias
[21:28:56] [PASSED] drm_test_buddy_fragmentation_performance
[21:28:56] ==================== [PASSED] drm_buddy ====================
[21:28:56] ============= drm_cmdline_parser (40 subtests) =============
[21:28:56] [PASSED] drm_test_cmdline_force_d_only
[21:28:56] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:28:56] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:28:56] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:28:56] [PASSED] drm_test_cmdline_force_e_only
[21:28:56] [PASSED] drm_test_cmdline_res
[21:28:56] [PASSED] drm_test_cmdline_res_vesa
[21:28:56] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:28:56] [PASSED] drm_test_cmdline_res_rblank
[21:28:56] [PASSED] drm_test_cmdline_res_bpp
[21:28:56] [PASSED] drm_test_cmdline_res_refresh
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:28:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:28:56] [PASSED] drm_test_cmdline_res_margins_force_on
[21:28:56] [PASSED] drm_test_cmdline_res_vesa_margins
[21:28:56] [PASSED] drm_test_cmdline_name
[21:28:56] [PASSED] drm_test_cmdline_name_bpp
[21:28:56] [PASSED] drm_test_cmdline_name_option
[21:28:56] [PASSED] drm_test_cmdline_name_bpp_option
[21:28:56] [PASSED] drm_test_cmdline_rotate_0
[21:28:56] [PASSED] drm_test_cmdline_rotate_90
[21:28:56] [PASSED] drm_test_cmdline_rotate_180
[21:28:56] [PASSED] drm_test_cmdline_rotate_270
[21:28:56] [PASSED] drm_test_cmdline_hmirror
[21:28:56] [PASSED] drm_test_cmdline_vmirror
[21:28:56] [PASSED] drm_test_cmdline_margin_options
[21:28:56] [PASSED] drm_test_cmdline_multiple_options
[21:28:56] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:28:56] [PASSED] drm_test_cmdline_extra_and_option
[21:28:56] [PASSED] drm_test_cmdline_freestanding_options
[21:28:56] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:28:56] [PASSED] drm_test_cmdline_panel_orientation
[21:28:56] ================ drm_test_cmdline_invalid =================
[21:28:56] [PASSED] margin_only
[21:28:56] [PASSED] interlace_only
[21:28:56] [PASSED] res_missing_x
[21:28:56] [PASSED] res_missing_y
[21:28:56] [PASSED] res_bad_y
[21:28:56] [PASSED] res_missing_y_bpp
[21:28:56] [PASSED] res_bad_bpp
[21:28:56] [PASSED] res_bad_refresh
[21:28:56] [PASSED] res_bpp_refresh_force_on_off
[21:28:56] [PASSED] res_invalid_mode
[21:28:56] [PASSED] res_bpp_wrong_place_mode
[21:28:56] [PASSED] name_bpp_refresh
[21:28:56] [PASSED] name_refresh
[21:28:56] [PASSED] name_refresh_wrong_mode
[21:28:56] [PASSED] name_refresh_invalid_mode
[21:28:56] [PASSED] rotate_multiple
[21:28:56] [PASSED] rotate_invalid_val
[21:28:56] [PASSED] rotate_truncated
[21:28:56] [PASSED] invalid_option
[21:28:56] [PASSED] invalid_tv_option
[21:28:56] [PASSED] truncated_tv_option
[21:28:56] ============ [PASSED] drm_test_cmdline_invalid =============
[21:28:56] =============== drm_test_cmdline_tv_options ===============
[21:28:56] [PASSED] NTSC
[21:28:56] [PASSED] NTSC_443
[21:28:56] [PASSED] NTSC_J
[21:28:56] [PASSED] PAL
[21:28:56] [PASSED] PAL_M
[21:28:56] [PASSED] PAL_N
[21:28:56] [PASSED] SECAM
[21:28:56] [PASSED] MONO_525
[21:28:56] [PASSED] MONO_625
[21:28:56] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:28:56] =============== [PASSED] drm_cmdline_parser ================
[21:28:56] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:28:56] [PASSED] drm_test_connector_hdmi_init_valid
[21:28:56] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:28:56] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:28:56] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:28:56] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:28:56] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:28:56] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:28:56] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:28:56] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:28:56] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:28:56] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:28:56] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:28:56] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:28:56] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:28:56] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:28:56] [PASSED] drm_test_connector_hdmi_init_null_product
[21:28:56] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:28:56] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:28:56] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:28:56] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:28:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:28:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:28:56] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:28:56] ========= drm_test_connector_hdmi_init_type_valid =========
[21:28:56] [PASSED] HDMI-A
[21:28:56] [PASSED] HDMI-B
[21:28:56] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:28:56] ======== drm_test_connector_hdmi_init_type_invalid ========
[21:28:56] [PASSED] Unknown
[21:28:56] [PASSED] VGA
[21:28:56] [PASSED] DVI-I
[21:28:56] [PASSED] DVI-D
[21:28:56] [PASSED] DVI-A
[21:28:56] [PASSED] Composite
[21:28:56] [PASSED] SVIDEO
[21:28:56] [PASSED] LVDS
[21:28:56] [PASSED] Component
[21:28:56] [PASSED] DIN
[21:28:56] [PASSED] DP
[21:28:56] [PASSED] TV
[21:28:56] [PASSED] eDP
[21:28:56] [PASSED] Virtual
[21:28:56] [PASSED] DSI
[21:28:56] [PASSED] DPI
[21:28:56] [PASSED] Writeback
[21:28:56] [PASSED] SPI
[21:28:56] [PASSED] USB
[21:28:56] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:28:56] ============ [PASSED] drmm_connector_hdmi_init =============
[21:28:56] ============= drmm_connector_init (3 subtests) =============
[21:28:56] [PASSED] drm_test_drmm_connector_init
[21:28:56] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:28:56] ========= drm_test_drmm_connector_init_type_valid =========
[21:28:56] [PASSED] Unknown
[21:28:56] [PASSED] VGA
[21:28:56] [PASSED] DVI-I
[21:28:56] [PASSED] DVI-D
[21:28:56] [PASSED] DVI-A
[21:28:56] [PASSED] Composite
[21:28:56] [PASSED] SVIDEO
[21:28:56] [PASSED] LVDS
[21:28:56] [PASSED] Component
[21:28:56] [PASSED] DIN
[21:28:56] [PASSED] DP
[21:28:56] [PASSED] HDMI-A
[21:28:56] [PASSED] HDMI-B
[21:28:56] [PASSED] TV
[21:28:56] [PASSED] eDP
[21:28:56] [PASSED] Virtual
[21:28:56] [PASSED] DSI
[21:28:56] [PASSED] DPI
[21:28:56] [PASSED] Writeback
[21:28:56] [PASSED] SPI
[21:28:56] [PASSED] USB
[21:28:56] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:28:56] =============== [PASSED] drmm_connector_init ===============
[21:28:56] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_init
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:28:56] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[21:28:56] [PASSED] Unknown
[21:28:56] [PASSED] VGA
[21:28:56] [PASSED] DVI-I
[21:28:56] [PASSED] DVI-D
[21:28:56] [PASSED] DVI-A
[21:28:56] [PASSED] Composite
[21:28:56] [PASSED] SVIDEO
[21:28:56] [PASSED] LVDS
[21:28:56] [PASSED] Component
[21:28:56] [PASSED] DIN
[21:28:56] [PASSED] DP
[21:28:56] [PASSED] HDMI-A
[21:28:56] [PASSED] HDMI-B
[21:28:56] [PASSED] TV
[21:28:56] [PASSED] eDP
[21:28:56] [PASSED] Virtual
[21:28:56] [PASSED] DSI
[21:28:56] [PASSED] DPI
[21:28:56] [PASSED] Writeback
[21:28:56] [PASSED] SPI
[21:28:56] [PASSED] USB
[21:28:56] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:28:56] ======== drm_test_drm_connector_dynamic_init_name =========
[21:28:56] [PASSED] Unknown
[21:28:56] [PASSED] VGA
[21:28:56] [PASSED] DVI-I
[21:28:56] [PASSED] DVI-D
[21:28:56] [PASSED] DVI-A
[21:28:56] [PASSED] Composite
[21:28:56] [PASSED] SVIDEO
[21:28:56] [PASSED] LVDS
[21:28:56] [PASSED] Component
[21:28:56] [PASSED] DIN
[21:28:56] [PASSED] DP
[21:28:56] [PASSED] HDMI-A
[21:28:56] [PASSED] HDMI-B
[21:28:56] [PASSED] TV
[21:28:56] [PASSED] eDP
[21:28:56] [PASSED] Virtual
[21:28:56] [PASSED] DSI
[21:28:56] [PASSED] DPI
[21:28:56] [PASSED] Writeback
[21:28:56] [PASSED] SPI
[21:28:56] [PASSED] USB
[21:28:56] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:28:56] =========== [PASSED] drm_connector_dynamic_init ============
[21:28:56] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:28:56] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:28:56] ======= drm_connector_dynamic_register (7 subtests) ========
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:28:56] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:28:56] ========= [PASSED] drm_connector_dynamic_register ==========
[21:28:56] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:28:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:28:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:28:56] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:28:56] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:28:56] ========== drm_test_get_tv_mode_from_name_valid ===========
[21:28:56] [PASSED] NTSC
[21:28:56] [PASSED] NTSC-443
[21:28:56] [PASSED] NTSC-J
[21:28:56] [PASSED] PAL
[21:28:56] [PASSED] PAL-M
[21:28:56] [PASSED] PAL-N
[21:28:56] [PASSED] SECAM
[21:28:56] [PASSED] Mono
[21:28:56] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:28:56] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:28:56] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:28:56] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:28:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:28:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:28:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:28:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:28:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:28:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:28:56] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[21:28:56] [PASSED] VIC 96
[21:28:56] [PASSED] VIC 97
[21:28:56] [PASSED] VIC 101
[21:28:56] [PASSED] VIC 102
[21:28:56] [PASSED] VIC 106
[21:28:56] [PASSED] VIC 107
[21:28:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:28:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:28:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:28:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:28:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:28:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:28:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:28:56] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:28:56] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[21:28:56] [PASSED] Automatic
[21:28:56] [PASSED] Full
[21:28:56] [PASSED] Limited 16:235
[21:28:56] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:28:56] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:28:56] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:28:56] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:28:56] === drm_test_drm_hdmi_connector_get_output_format_name ====
[21:28:56] [PASSED] RGB
[21:28:56] [PASSED] YUV 4:2:0
[21:28:56] [PASSED] YUV 4:2:2
[21:28:56] [PASSED] YUV 4:4:4
[21:28:56] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:28:56] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:28:56] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:28:56] ============= drm_damage_helper (21 subtests) ==============
[21:28:56] [PASSED] drm_test_damage_iter_no_damage
[21:28:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:28:56] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:28:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:28:56] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:28:56] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:28:56] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:28:56] [PASSED] drm_test_damage_iter_simple_damage
[21:28:56] [PASSED] drm_test_damage_iter_single_damage
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:28:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:28:56] [PASSED] drm_test_damage_iter_damage
[21:28:56] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:28:56] [PASSED] drm_test_damage_iter_damage_one_outside
[21:28:56] [PASSED] drm_test_damage_iter_damage_src_moved
[21:28:56] [PASSED] drm_test_damage_iter_damage_not_visible
[21:28:56] ================ [PASSED] drm_damage_helper ================
[21:28:56] ============== drm_dp_mst_helper (3 subtests) ==============
[21:28:56] ============== drm_test_dp_mst_calc_pbn_mode ==============
[21:28:56] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:28:56] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:28:56] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:28:56] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:28:56] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:28:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:28:56] ============== drm_test_dp_mst_calc_pbn_div ===============
[21:28:56] [PASSED] Link rate 2000000 lane count 4
[21:28:56] [PASSED] Link rate 2000000 lane count 2
[21:28:56] [PASSED] Link rate 2000000 lane count 1
[21:28:56] [PASSED] Link rate 1350000 lane count 4
[21:28:56] [PASSED] Link rate 1350000 lane count 2
[21:28:56] [PASSED] Link rate 1350000 lane count 1
[21:28:56] [PASSED] Link rate 1000000 lane count 4
[21:28:56] [PASSED] Link rate 1000000 lane count 2
[21:28:56] [PASSED] Link rate 1000000 lane count 1
[21:28:56] [PASSED] Link rate 810000 lane count 4
[21:28:56] [PASSED] Link rate 810000 lane count 2
[21:28:56] [PASSED] Link rate 810000 lane count 1
[21:28:56] [PASSED] Link rate 540000 lane count 4
[21:28:56] [PASSED] Link rate 540000 lane count 2
[21:28:56] [PASSED] Link rate 540000 lane count 1
[21:28:56] [PASSED] Link rate 270000 lane count 4
[21:28:56] [PASSED] Link rate 270000 lane count 2
[21:28:56] [PASSED] Link rate 270000 lane count 1
[21:28:56] [PASSED] Link rate 162000 lane count 4
[21:28:56] [PASSED] Link rate 162000 lane count 2
[21:28:56] [PASSED] Link rate 162000 lane count 1
[21:28:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:28:56] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[21:28:56] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:28:56] [PASSED] DP_POWER_UP_PHY with port number
[21:28:56] [PASSED] DP_POWER_DOWN_PHY with port number
[21:28:56] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:28:56] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:28:56] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:28:56] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:28:56] [PASSED] DP_QUERY_PAYLOAD with port number
[21:28:56] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:28:56] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:28:56] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:28:56] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:28:56] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:28:56] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:28:56] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:28:56] [PASSED] DP_REMOTE_I2C_READ with port number
[21:28:56] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:28:56] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:28:56] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:28:56] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:28:56] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:28:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:28:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:28:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:28:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:28:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:28:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:28:56] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:28:56] ================ [PASSED] drm_dp_mst_helper ================
[21:28:56] ================== drm_exec (7 subtests) ===================
[21:28:56] [PASSED] sanitycheck
[21:28:56] [PASSED] test_lock
[21:28:56] [PASSED] test_lock_unlock
[21:28:56] [PASSED] test_duplicates
[21:28:56] [PASSED] test_prepare
[21:28:56] [PASSED] test_prepare_array
[21:28:56] [PASSED] test_multiple_loops
[21:28:56] ==================== [PASSED] drm_exec =====================
[21:28:56] =========== drm_format_helper_test (17 subtests) ===========
[21:28:56] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:28:56] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:28:56] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:28:56] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:28:56] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:28:56] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:28:56] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:28:56] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:28:56] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:28:56] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:28:56] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:28:56] ============== drm_test_fb_xrgb8888_to_mono ===============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:28:56] ==================== drm_test_fb_swab =====================
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ================ [PASSED] drm_test_fb_swab =================
[21:28:56] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:28:56] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[21:28:56] [PASSED] single_pixel_source_buffer
[21:28:56] [PASSED] single_pixel_clip_rectangle
[21:28:56] [PASSED] well_known_colors
[21:28:56] [PASSED] destination_pitch
[21:28:56] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:28:56] ================= drm_test_fb_clip_offset =================
[21:28:56] [PASSED] pass through
[21:28:56] [PASSED] horizontal offset
[21:28:56] [PASSED] vertical offset
[21:28:56] [PASSED] horizontal and vertical offset
[21:28:56] [PASSED] horizontal offset (custom pitch)
[21:28:56] [PASSED] vertical offset (custom pitch)
[21:28:56] [PASSED] horizontal and vertical offset (custom pitch)
[21:28:56] ============= [PASSED] drm_test_fb_clip_offset =============
[21:28:56] =================== drm_test_fb_memcpy ====================
[21:28:56] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:28:56] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:28:56] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:28:56] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:28:56] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:28:56] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:28:56] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:28:56] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:28:56] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:28:56] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:28:56] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:28:56] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:28:56] =============== [PASSED] drm_test_fb_memcpy ================
[21:28:56] ============= [PASSED] drm_format_helper_test ==============
[21:28:56] ================= drm_format (18 subtests) =================
[21:28:56] [PASSED] drm_test_format_block_width_invalid
[21:28:56] [PASSED] drm_test_format_block_width_one_plane
[21:28:56] [PASSED] drm_test_format_block_width_two_plane
[21:28:56] [PASSED] drm_test_format_block_width_three_plane
[21:28:56] [PASSED] drm_test_format_block_width_tiled
[21:28:56] [PASSED] drm_test_format_block_height_invalid
[21:28:56] [PASSED] drm_test_format_block_height_one_plane
[21:28:56] [PASSED] drm_test_format_block_height_two_plane
[21:28:56] [PASSED] drm_test_format_block_height_three_plane
[21:28:56] [PASSED] drm_test_format_block_height_tiled
[21:28:56] [PASSED] drm_test_format_min_pitch_invalid
[21:28:56] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:28:56] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:28:56] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:28:56] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:28:56] [PASSED] drm_test_format_min_pitch_two_plane
[21:28:56] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:28:56] [PASSED] drm_test_format_min_pitch_tiled
[21:28:56] =================== [PASSED] drm_format ====================
[21:28:56] ============== drm_framebuffer (10 subtests) ===============
[21:28:56] ========== drm_test_framebuffer_check_src_coords ==========
[21:28:56] [PASSED] Success: source fits into fb
[21:28:56] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:28:56] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:28:56] [PASSED] Fail: overflowing fb with source width
[21:28:56] [PASSED] Fail: overflowing fb with source height
[21:28:56] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:28:56] [PASSED] drm_test_framebuffer_cleanup
[21:28:56] =============== drm_test_framebuffer_create ===============
[21:28:56] [PASSED] ABGR8888 normal sizes
[21:28:56] [PASSED] ABGR8888 max sizes
[21:28:56] [PASSED] ABGR8888 pitch greater than min required
[21:28:56] [PASSED] ABGR8888 pitch less than min required
[21:28:56] [PASSED] ABGR8888 Invalid width
[21:28:56] [PASSED] ABGR8888 Invalid buffer handle
[21:28:56] [PASSED] No pixel format
[21:28:56] [PASSED] ABGR8888 Width 0
[21:28:56] [PASSED] ABGR8888 Height 0
[21:28:56] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:28:56] [PASSED] ABGR8888 Large buffer offset
[21:28:56] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:28:56] [PASSED] ABGR8888 Invalid flag
[21:28:56] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:28:56] [PASSED] ABGR8888 Valid buffer modifier
[21:28:56] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:28:56] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] NV12 Normal sizes
[21:28:56] [PASSED] NV12 Max sizes
[21:28:56] [PASSED] NV12 Invalid pitch
[21:28:56] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:28:56] [PASSED] NV12 different modifier per-plane
[21:28:56] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:28:56] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] NV12 Modifier for inexistent plane
[21:28:56] [PASSED] NV12 Handle for inexistent plane
[21:28:56] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:28:56] [PASSED] YVU420 Normal sizes
[21:28:56] [PASSED] YVU420 Max sizes
[21:28:56] [PASSED] YVU420 Invalid pitch
[21:28:56] [PASSED] YVU420 Different pitches
[21:28:56] [PASSED] YVU420 Different buffer offsets/pitches
[21:28:56] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:28:56] [PASSED] YVU420 Valid modifier
[21:28:56] [PASSED] YVU420 Different modifiers per plane
[21:28:56] [PASSED] YVU420 Modifier for inexistent plane
[21:28:56] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:28:56] [PASSED] X0L2 Normal sizes
[21:28:56] [PASSED] X0L2 Max sizes
[21:28:56] [PASSED] X0L2 Invalid pitch
[21:28:56] [PASSED] X0L2 Pitch greater than minimum required
[21:28:56] [PASSED] X0L2 Handle for inexistent plane
[21:28:56] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:28:56] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:28:56] [PASSED] X0L2 Valid modifier
[21:28:56] [PASSED] X0L2 Modifier for inexistent plane
[21:28:56] =========== [PASSED] drm_test_framebuffer_create ===========
[21:28:56] [PASSED] drm_test_framebuffer_free
[21:28:56] [PASSED] drm_test_framebuffer_init
[21:28:56] [PASSED] drm_test_framebuffer_init_bad_format
[21:28:56] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:28:56] [PASSED] drm_test_framebuffer_lookup
[21:28:56] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:28:56] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:28:56] ================= [PASSED] drm_framebuffer =================
[21:28:56] ================ drm_gem_shmem (8 subtests) ================
[21:28:56] [PASSED] drm_gem_shmem_test_obj_create
[21:28:56] [PASSED] drm_gem_shmem_test_obj_create_private
[21:28:56] [PASSED] drm_gem_shmem_test_pin_pages
[21:28:56] [PASSED] drm_gem_shmem_test_vmap
[21:28:56] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:28:56] [PASSED] drm_gem_shmem_test_get_sg_table
[21:28:56] [PASSED] drm_gem_shmem_test_madvise
[21:28:56] [PASSED] drm_gem_shmem_test_purge
[21:28:56] ================== [PASSED] drm_gem_shmem ==================
[21:28:56] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:28:56] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[21:28:56] [PASSED] Automatic
[21:28:56] [PASSED] Full
[21:28:56] [PASSED] Limited 16:235
[21:28:56] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:28:56] [PASSED] drm_test_check_disable_connector
[21:28:56] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:28:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:28:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:28:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:28:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:28:56] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:28:56] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:28:56] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:28:56] [PASSED] drm_test_check_output_bpc_dvi
[21:28:56] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:28:56] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:28:56] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:28:56] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:28:56] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:28:56] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:28:56] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:28:56] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:28:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:28:56] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:28:56] [PASSED] drm_test_check_broadcast_rgb_value
[21:28:56] [PASSED] drm_test_check_bpc_8_value
[21:28:56] [PASSED] drm_test_check_bpc_10_value
[21:28:56] [PASSED] drm_test_check_bpc_12_value
[21:28:56] [PASSED] drm_test_check_format_value
[21:28:56] [PASSED] drm_test_check_tmds_char_value
[21:28:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:28:56] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:28:56] [PASSED] drm_test_check_mode_valid
[21:28:56] [PASSED] drm_test_check_mode_valid_reject
[21:28:56] [PASSED] drm_test_check_mode_valid_reject_rate
[21:28:56] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:28:56] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:28:56] ================= drm_managed (2 subtests) =================
[21:28:56] [PASSED] drm_test_managed_release_action
[21:28:56] [PASSED] drm_test_managed_run_action
[21:28:56] =================== [PASSED] drm_managed ===================
[21:28:56] =================== drm_mm (6 subtests) ====================
[21:28:56] [PASSED] drm_test_mm_init
[21:28:56] [PASSED] drm_test_mm_debug
[21:28:56] [PASSED] drm_test_mm_align32
[21:28:56] [PASSED] drm_test_mm_align64
[21:28:56] [PASSED] drm_test_mm_lowest
[21:28:56] [PASSED] drm_test_mm_highest
[21:28:56] ===================== [PASSED] drm_mm ======================
[21:28:56] ============= drm_modes_analog_tv (5 subtests) =============
[21:28:56] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:28:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:28:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:28:56] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:28:56] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:28:56] =============== [PASSED] drm_modes_analog_tv ===============
[21:28:56] ============== drm_plane_helper (2 subtests) ===============
[21:28:56] =============== drm_test_check_plane_state ================
[21:28:56] [PASSED] clipping_simple
[21:28:56] [PASSED] clipping_rotate_reflect
[21:28:56] [PASSED] positioning_simple
[21:28:56] [PASSED] upscaling
[21:28:56] [PASSED] downscaling
[21:28:56] [PASSED] rounding1
[21:28:56] [PASSED] rounding2
[21:28:56] [PASSED] rounding3
[21:28:56] [PASSED] rounding4
[21:28:56] =========== [PASSED] drm_test_check_plane_state ============
[21:28:56] =========== drm_test_check_invalid_plane_state ============
[21:28:56] [PASSED] positioning_invalid
[21:28:56] [PASSED] upscaling_invalid
[21:28:56] [PASSED] downscaling_invalid
[21:28:56] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:28:56] ================ [PASSED] drm_plane_helper =================
[21:28:56] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:28:56] ====== drm_test_connector_helper_tv_get_modes_check =======
[21:28:56] [PASSED] None
[21:28:56] [PASSED] PAL
[21:28:56] [PASSED] NTSC
[21:28:56] [PASSED] Both, NTSC Default
[21:28:56] [PASSED] Both, PAL Default
[21:28:56] [PASSED] Both, NTSC Default, with PAL on command-line
[21:28:56] [PASSED] Both, PAL Default, with NTSC on command-line
[21:28:56] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:28:56] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:28:56] ================== drm_rect (9 subtests) ===================
[21:28:56] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:28:56] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:28:56] [PASSED] drm_test_rect_clip_scaled_clipped
[21:28:56] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:28:56] ================= drm_test_rect_intersect =================
[21:28:56] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:28:56] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:28:56] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:28:56] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:28:56] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:28:56] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:28:56] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:28:56] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:28:56] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:28:56] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:28:56] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:28:56] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:28:56] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:28:56] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:28:56] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:28:56] ============= [PASSED] drm_test_rect_intersect =============
[21:28:56] ================ drm_test_rect_calc_hscale ================
[21:28:56] [PASSED] normal use
[21:28:56] [PASSED] out of max range
[21:28:56] [PASSED] out of min range
[21:28:56] [PASSED] zero dst
[21:28:56] [PASSED] negative src
[21:28:56] [PASSED] negative dst
[21:28:56] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:28:56] ================ drm_test_rect_calc_vscale ================
[21:28:56] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[21:28:56] [PASSED] out of max range
[21:28:56] [PASSED] out of min range
[21:28:56] [PASSED] zero dst
[21:28:56] [PASSED] negative src
[21:28:56] [PASSED] negative dst
[21:28:56] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:28:56] ================== drm_test_rect_rotate ===================
[21:28:56] [PASSED] reflect-x
[21:28:56] [PASSED] reflect-y
[21:28:56] [PASSED] rotate-0
[21:28:56] [PASSED] rotate-90
[21:28:56] [PASSED] rotate-180
[21:28:56] [PASSED] rotate-270
[21:28:56] ============== [PASSED] drm_test_rect_rotate ===============
[21:28:56] ================ drm_test_rect_rotate_inv =================
[21:28:56] [PASSED] reflect-x
[21:28:56] [PASSED] reflect-y
[21:28:56] [PASSED] rotate-0
[21:28:56] [PASSED] rotate-90
[21:28:56] [PASSED] rotate-180
[21:28:56] [PASSED] rotate-270
[21:28:56] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:28:56] ==================== [PASSED] drm_rect =====================
[21:28:56] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:28:56] ============ drm_test_sysfb_build_fourcc_list =============
[21:28:56] [PASSED] no native formats
[21:28:56] [PASSED] XRGB8888 as native format
[21:28:56] [PASSED] remove duplicates
[21:28:56] [PASSED] convert alpha formats
[21:28:56] [PASSED] random formats
[21:28:56] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:28:56] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:28:56] ============================================================
[21:28:56] Testing complete. Ran 622 tests: passed: 622
[21:28:56] Elapsed time: 31.988s total, 1.638s configuring, 29.882s building, 0.416s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:28:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:28:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:29:07] Starting KUnit Kernel (1/1)...
[21:29:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:29:07] ================= ttm_device (5 subtests) ==================
[21:29:07] [PASSED] ttm_device_init_basic
[21:29:07] [PASSED] ttm_device_init_multiple
[21:29:07] [PASSED] ttm_device_fini_basic
[21:29:07] [PASSED] ttm_device_init_no_vma_man
[21:29:07] ================== ttm_device_init_pools ==================
[21:29:07] [PASSED] No DMA allocations, no DMA32 required
[21:29:07] [PASSED] DMA allocations, DMA32 required
[21:29:07] [PASSED] No DMA allocations, DMA32 required
[21:29:07] [PASSED] DMA allocations, no DMA32 required
[21:29:07] ============== [PASSED] ttm_device_init_pools ==============
[21:29:07] =================== [PASSED] ttm_device ====================
[21:29:07] ================== ttm_pool (8 subtests) ===================
[21:29:07] ================== ttm_pool_alloc_basic ===================
[21:29:07] [PASSED] One page
[21:29:07] [PASSED] More than one page
[21:29:07] [PASSED] Above the allocation limit
[21:29:07] [PASSED] One page, with coherent DMA mappings enabled
[21:29:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:29:07] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:29:07] ============== ttm_pool_alloc_basic_dma_addr ==============
[21:29:07] [PASSED] One page
[21:29:07] [PASSED] More than one page
[21:29:07] [PASSED] Above the allocation limit
[21:29:07] [PASSED] One page, with coherent DMA mappings enabled
[21:29:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:29:07] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:29:07] [PASSED] ttm_pool_alloc_order_caching_match
[21:29:07] [PASSED] ttm_pool_alloc_caching_mismatch
[21:29:07] [PASSED] ttm_pool_alloc_order_mismatch
[21:29:07] [PASSED] ttm_pool_free_dma_alloc
[21:29:07] [PASSED] ttm_pool_free_no_dma_alloc
[21:29:07] [PASSED] ttm_pool_fini_basic
[21:29:07] ==================== [PASSED] ttm_pool =====================
[21:29:07] ================ ttm_resource (8 subtests) =================
[21:29:07] ================= ttm_resource_init_basic =================
[21:29:07] [PASSED] Init resource in TTM_PL_SYSTEM
[21:29:07] [PASSED] Init resource in TTM_PL_VRAM
[21:29:07] [PASSED] Init resource in a private placement
[21:29:07] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:29:07] ============= [PASSED] ttm_resource_init_basic =============
[21:29:07] [PASSED] ttm_resource_init_pinned
[21:29:07] [PASSED] ttm_resource_fini_basic
[21:29:07] [PASSED] ttm_resource_manager_init_basic
[21:29:07] [PASSED] ttm_resource_manager_usage_basic
[21:29:07] [PASSED] ttm_resource_manager_set_used_basic
[21:29:07] [PASSED] ttm_sys_man_alloc_basic
[21:29:07] [PASSED] ttm_sys_man_free_basic
[21:29:07] ================== [PASSED] ttm_resource ===================
[21:29:07] =================== ttm_tt (15 subtests) ===================
[21:29:07] ==================== ttm_tt_init_basic ====================
[21:29:07] [PASSED] Page-aligned size
[21:29:07] [PASSED] Extra pages requested
[21:29:07] ================ [PASSED] ttm_tt_init_basic ================
[21:29:07] [PASSED] ttm_tt_init_misaligned
[21:29:07] [PASSED] ttm_tt_fini_basic
[21:29:07] [PASSED] ttm_tt_fini_sg
[21:29:07] [PASSED] ttm_tt_fini_shmem
[21:29:07] [PASSED] ttm_tt_create_basic
[21:29:07] [PASSED] ttm_tt_create_invalid_bo_type
[21:29:07] [PASSED] ttm_tt_create_ttm_exists
[21:29:07] [PASSED] ttm_tt_create_failed
[21:29:07] [PASSED] ttm_tt_destroy_basic
[21:29:07] [PASSED] ttm_tt_populate_null_ttm
[21:29:07] [PASSED] ttm_tt_populate_populated_ttm
[21:29:07] [PASSED] ttm_tt_unpopulate_basic
[21:29:07] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:29:07] [PASSED] ttm_tt_swapin_basic
[21:29:07] ===================== [PASSED] ttm_tt ======================
[21:29:07] =================== ttm_bo (14 subtests) ===================
[21:29:07] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[21:29:07] [PASSED] Cannot be interrupted and sleeps
[21:29:07] [PASSED] Cannot be interrupted, locks straight away
[21:29:07] [PASSED] Can be interrupted, sleeps
[21:29:07] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:29:07] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:29:07] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:29:07] [PASSED] ttm_bo_reserve_double_resv
[21:29:07] [PASSED] ttm_bo_reserve_interrupted
[21:29:07] [PASSED] ttm_bo_reserve_deadlock
[21:29:07] [PASSED] ttm_bo_unreserve_basic
[21:29:07] [PASSED] ttm_bo_unreserve_pinned
[21:29:07] [PASSED] ttm_bo_unreserve_bulk
[21:29:07] [PASSED] ttm_bo_fini_basic
[21:29:07] [PASSED] ttm_bo_fini_shared_resv
[21:29:07] [PASSED] ttm_bo_pin_basic
[21:29:07] [PASSED] ttm_bo_pin_unpin_resource
[21:29:07] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:29:07] ===================== [PASSED] ttm_bo ======================
[21:29:07] ============== ttm_bo_validate (21 subtests) ===============
[21:29:07] ============== ttm_bo_init_reserved_sys_man ===============
[21:29:07] [PASSED] Buffer object for userspace
[21:29:07] [PASSED] Kernel buffer object
[21:29:07] [PASSED] Shared buffer object
[21:29:07] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:29:07] ============== ttm_bo_init_reserved_mock_man ==============
[21:29:07] [PASSED] Buffer object for userspace
[21:29:07] [PASSED] Kernel buffer object
[21:29:07] [PASSED] Shared buffer object
[21:29:07] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:29:07] [PASSED] ttm_bo_init_reserved_resv
[21:29:07] ================== ttm_bo_validate_basic ==================
[21:29:07] [PASSED] Buffer object for userspace
[21:29:07] [PASSED] Kernel buffer object
[21:29:07] [PASSED] Shared buffer object
[21:29:07] ============== [PASSED] ttm_bo_validate_basic ==============
[21:29:07] [PASSED] ttm_bo_validate_invalid_placement
[21:29:07] ============= ttm_bo_validate_same_placement ==============
[21:29:07] [PASSED] System manager
[21:29:07] [PASSED] VRAM manager
[21:29:07] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:29:07] [PASSED] ttm_bo_validate_failed_alloc
[21:29:07] [PASSED] ttm_bo_validate_pinned
[21:29:07] [PASSED] ttm_bo_validate_busy_placement
[21:29:07] ================ ttm_bo_validate_multihop =================
[21:29:07] [PASSED] Buffer object for userspace
[21:29:07] [PASSED] Kernel buffer object
[21:29:07] [PASSED] Shared buffer object
[21:29:07] ============ [PASSED] ttm_bo_validate_multihop =============
[21:29:07] ========== ttm_bo_validate_no_placement_signaled ==========
[21:29:07] [PASSED] Buffer object in system domain, no page vector
[21:29:07] [PASSED] Buffer object in system domain with an existing page vector
[21:29:07] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:29:07] ======== ttm_bo_validate_no_placement_not_signaled ========
[21:29:07] [PASSED] Buffer object for userspace
[21:29:07] [PASSED] Kernel buffer object
[21:29:07] [PASSED] Shared buffer object
[21:29:07] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:29:07] [PASSED] ttm_bo_validate_move_fence_signaled
[21:29:07] ========= ttm_bo_validate_move_fence_not_signaled =========
[21:29:07] [PASSED] Waits for GPU
[21:29:07] [PASSED] Tries to lock straight away
[21:29:07] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:29:07] [PASSED] ttm_bo_validate_happy_evict
[21:29:07] [PASSED] ttm_bo_validate_all_pinned_evict
[21:29:07] [PASSED] ttm_bo_validate_allowed_only_evict
[21:29:07] [PASSED] ttm_bo_validate_deleted_evict
[21:29:07] [PASSED] ttm_bo_validate_busy_domain_evict
[21:29:07] [PASSED] ttm_bo_validate_evict_gutting
[21:29:07] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:29:07] ================= [PASSED] ttm_bo_validate =================
[21:29:07] ============================================================
[21:29:07] Testing complete. Ran 101 tests: passed: 101
[21:29:07] Elapsed time: 10.966s total, 1.625s configuring, 9.124s building, 0.187s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* ✓ Xe.CI.BAT: success for drm/xe: Tile address change
2025-11-07 18:23 [PATCH 0/2] drm/xe: Tile address change Lucas De Marchi
` (2 preceding siblings ...)
2025-11-07 21:29 ` ✓ CI.KUnit: success for drm/xe: Tile address change Patchwork
@ 2025-11-07 22:29 ` Patchwork
2025-11-09 4:55 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-10 17:43 ` [PATCH 0/2] " Lucas De Marchi
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-11-07 22:29 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 988 bytes --]
== Series Details ==
Series: drm/xe: Tile address change
URL : https://patchwork.freedesktop.org/series/157254/
State : success
== Summary ==
CI Bug Log - changes from xe-4073-4dff427fe8bbfd0bdbf7935d23a2aba0c350ab2d_BAT -> xe-pw-157254v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8613 -> IGT_8614
* Linux: xe-4073-4dff427fe8bbfd0bdbf7935d23a2aba0c350ab2d -> xe-pw-157254v1
IGT_8613: b542242f5b116e3b554b4068ef5dfa4451075b2b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8614: 8614
xe-4073-4dff427fe8bbfd0bdbf7935d23a2aba0c350ab2d: 4dff427fe8bbfd0bdbf7935d23a2aba0c350ab2d
xe-pw-157254v1: 157254v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157254v1/index.html
[-- Attachment #2: Type: text/html, Size: 1550 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread* ✗ Xe.CI.Full: failure for drm/xe: Tile address change
2025-11-07 18:23 [PATCH 0/2] drm/xe: Tile address change Lucas De Marchi
` (3 preceding siblings ...)
2025-11-07 22:29 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-11-09 4:55 ` Patchwork
2025-11-10 17:43 ` [PATCH 0/2] " Lucas De Marchi
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2025-11-09 4:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 358 bytes --]
== Series Details ==
Series: drm/xe: Tile address change
URL : https://patchwork.freedesktop.org/series/157254/
State : failure
== Summary ==
ERROR: The runconfig 'xe-4073-4dff427fe8bbfd0bdbf7935d23a2aba0c350ab2d_FULL' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157254v1/index.html
[-- Attachment #2: Type: text/html, Size: 923 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 0/2] drm/xe: Tile address change
2025-11-07 18:23 [PATCH 0/2] drm/xe: Tile address change Lucas De Marchi
` (4 preceding siblings ...)
2025-11-09 4:55 ` ✗ Xe.CI.Full: failure " Patchwork
@ 2025-11-10 17:43 ` Lucas De Marchi
5 siblings, 0 replies; 8+ messages in thread
From: Lucas De Marchi @ 2025-11-10 17:43 UTC (permalink / raw)
To: intel-xe, Lucas De Marchi; +Cc: fei.yang, Matt Roper
On Fri, 07 Nov 2025 10:23:43 -0800, Lucas De Marchi wrote:
> Same patch as https://lore.kernel.org/all/20250930232645.600251-1-fei.yang@intel.com/
> but with the additional suggestions taken care of, one of them as
> a separate patch.
>
>
Merged to drm-xe-next, thanks!
[1/2] drm/xe: Use SG_TILE_ADDR_RANGE instead of TILE_ADDR_RANGE
commit: 84a6fc4c9fb95c7abdc2c749e7d9d8947061b259
[2/2] drm/xe/vram: Move forcewake down to get_flat_ccs_offset()
commit: 3389c2be7fa0733b225c5676b1eaa87927745409
--
Lucas De Marchi
^ permalink raw reply [flat|nested] 8+ messages in thread