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* [PATCH v3] drm/xe: expose PAT software table via debugfs
@ 2025-11-14 22:40 Xin Wang
  2025-11-15  0:23 ` ✗ CI.checkpatch: warning for drm/xe: expose PAT software table via debugfs (rev3) Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Xin Wang @ 2025-11-14 22:40 UTC (permalink / raw)
  To: intel-xe; +Cc: shuicheng.lin, alex.zuo, Xin Wang, Matt Roper, Jonathan Cavitt

The existing "pat" debugfs node dumps the live PAT registers. Under SR-IOV
the VF cannot touch those registers, so the file vanishes and users lose
all PAT visibility. Add a VF-safe "pat_sw_config" entry to the VF-safe
debugfs list. It prints the cached PAT table the driver programmed, rather
than poking HW, so PF and VF instances present the same view.

This lets IGT and other tools query the PAT configuration without carrying
platform-specific tables or mirroring kernel logic.

v2: (Jonathan)
- Only append "(* = reserved entry)" to the PAT table header on Xe2+
platforms where it actually applies.
- Deduplicate the PTA/ATS mode printing by introducing the small
drm_printf_pat_mode() helper macro.

v3: (Matt)
- Print IDX[XE_CACHE_NONE_COMPRESSION] on every Xe2+ platform so the dump
always reflects the value the driver might use (even if it defaults to 0)
and future IP revisions don’t need extra condition tweaks.

Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_debugfs.c |  1 +
 drivers/gpu/drm/xe/xe_pat.c        | 87 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_pat.h        |  1 +
 3 files changed, 89 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index e4fd632f43cf..ec279f005b10 100644
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -220,6 +220,7 @@ static const struct drm_info_list vf_safe_debugfs_list[] = {
 	{ "default_lrc_vcs", .show = xe_gt_debugfs_show_with_rpm, .data = vcs_default_lrc },
 	{ "default_lrc_vecs", .show = xe_gt_debugfs_show_with_rpm, .data = vecs_default_lrc },
 	{ "hwconfig", .show = xe_gt_debugfs_show_with_rpm, .data = hwconfig },
+	{ "pat_sw_config", .show = xe_gt_debugfs_simple_show, .data = xe_pat_dump_sw_config },
 };
 
 /* everything else should be added here */
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 68171cceea18..e16ee7132dfc 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -578,3 +578,90 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
 
 	return xe->pat.ops->dump(gt, p);
 }
+
+#define drm_printf_pat_mode(p, name, pat) \
+	{ \
+		drm_printf(p, name "= [ %u, %u, %u, %u, %u, %u ]  (%#8x)\n", \
+		   !!(pat & XE2_NO_PROMOTE), \
+		   !!(pat & XE2_COMP_EN), \
+		   REG_FIELD_GET(XE2_L3_CLOS, pat), \
+		   REG_FIELD_GET(XE2_L3_POLICY, pat), \
+		   REG_FIELD_GET(XE2_L4_POLICY, pat), \
+		   REG_FIELD_GET(XE2_COH_MODE, pat), \
+		   pat); \
+	}
+/**
+ * xe_pat_dump_sw_config() - Dump the software-configured GT PAT table into a drm printer.
+ * @gt: the &xe_gt
+ * @p: the &drm_printer
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
+{
+	struct xe_device *xe = gt_to_xe(gt);
+
+	if (!xe->pat.table || !xe->pat.n_entries)
+		return -EOPNOTSUPP;
+
+	drm_printf(p, "PAT table:%s\n", GRAPHICS_VER(xe) >= 20 ? " (* = reserved entry)" : "");
+	for (u32 i = 0; i < xe->pat.n_entries; i++) {
+		u32 pat = xe->pat.table[i].value;
+
+		if (GRAPHICS_VER(xe) >= 20) {
+			drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u, %u ]  (%#8x)%s\n", i,
+				   !!(pat & XE2_NO_PROMOTE),
+				   !!(pat & XE2_COMP_EN),
+				   REG_FIELD_GET(XE2_L3_CLOS, pat),
+				   REG_FIELD_GET(XE2_L3_POLICY, pat),
+				   REG_FIELD_GET(XE2_L4_POLICY, pat),
+				   REG_FIELD_GET(XE2_COH_MODE, pat),
+				   pat, xe->pat.table[i].valid ? "" : " *");
+		} else if (xe->info.platform == XE_METEORLAKE) {
+			drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i,
+				   REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat),
+				   REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat);
+		} else if (xe->info.platform == XE_PVC) {
+			drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i,
+				   REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat),
+				   REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat);
+		} else if (xe->info.platform == XE_DG2) {
+			u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);
+
+			drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i,
+				   XELP_MEM_TYPE_STR_MAP[mem_type], pat);
+		} else if (GRAPHICS_VERx100(xe) <= 1210) {
+			u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);
+
+			drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i,
+				   XELP_MEM_TYPE_STR_MAP[mem_type], pat);
+		} else {
+			return -EOPNOTSUPP;
+		}
+	}
+
+	if (xe->pat.pat_pta) {
+		u32 pat = xe->pat.pat_pta->value;
+
+		drm_printf(p, "Page Table Access:\n");
+		drm_printf_pat_mode(p, "PTA_MODE", pat);
+	}
+
+	if (xe->pat.pat_ats) {
+		u32 pat = xe->pat.pat_ats->value;
+
+		drm_printf(p, "PCIe ATS response:\n");
+		drm_printf_pat_mode(p, "ATS_MODE", pat);
+	}
+
+	drm_printf(p, "Cache Level:\n");
+	drm_printf(p, "IDX[XE_CACHE_NONE] = %d\n", xe->pat.idx[XE_CACHE_NONE]);
+	drm_printf(p, "IDX[XE_CACHE_WT] = %d\n", xe->pat.idx[XE_CACHE_WT]);
+	drm_printf(p, "IDX[XE_CACHE_WB] = %d\n", xe->pat.idx[XE_CACHE_WB]);
+	if (GRAPHICS_VER(xe) >= 20) {
+		drm_printf(p, "IDX[XE_CACHE_NONE_COMPRESSION] = %d\n",
+			   xe->pat.idx[XE_CACHE_NONE_COMPRESSION]);
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index 05dae03a5f54..4a3045f74bfe 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -49,6 +49,7 @@ void xe_pat_init_early(struct xe_device *xe);
 void xe_pat_init(struct xe_gt *gt);
 
 int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);
+int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p);
 
 /**
  * xe_pat_index_get_coh_mode - Extract the coherency mode for the given
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-11-17  8:44 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-14 22:40 [PATCH v3] drm/xe: expose PAT software table via debugfs Xin Wang
2025-11-15  0:23 ` ✗ CI.checkpatch: warning for drm/xe: expose PAT software table via debugfs (rev3) Patchwork
2025-11-15  0:24 ` ✓ CI.KUnit: success " Patchwork
2025-11-15  1:36 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-15 12:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-17  8:44 ` [PATCH v3] drm/xe: expose PAT software table via debugfs Jani Nikula

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