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This is not true on BMG where all the ports - including the PORT_TC1..4 TypeC DDI ports - are connected to a non-TypeC PHY. For these ports intel_port_to_tc() returns TC_PORT_NONE, which results in an incorrect port -> PLL ID mapping. Fix this up by using the expected PORT_TC1..4 port -> TC_PORT_1..4 tc_port mapping on BMG as well. Fixes: ca1eda5cd476c ("drm/i915/cx0: Add MTL+ .get_dplls hook") Cc: Suraj Kandpal Reviewed-by: Mika Kahola Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 +++++---- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 96fcad6dbb2f4..8471bdab5c62f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4294,9 +4294,10 @@ static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, } /* - * Get the configuration for either a port using a C10 PHY PLL, or in the case of - * the PTL port B eDP on TypeC PHY case the configuration of a port using a C20 - * PHY PLL. + * Get the configuration for either a port using a C10 PHY PLL, or a port using a + * C20 PHY PLL in the cases of: + * - BMG port A/B + * - PTL port B eDP over TypeC PHY */ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6d7d5394713d6..8ae8cc7ad79d3 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -206,7 +206,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port) { if (port >= PORT_TC1) - return icl_tc_port_to_pll_id(intel_port_to_tc(display, port)); + return icl_tc_port_to_pll_id(port - PORT_TC1 + TC_PORT_1); switch (port) { case PORT_A: @@ -3507,9 +3507,10 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, } /* - * Get the PLL for either a port using a C10 PHY PLL, or in the - * PTL port B eDP over TypeC PHY case, the PLL for a port using - * a C20 PHY PLL. + * Get the PLL for either a port using a C10 PHY PLL, or for a port using a + * C20 PHY PLL in the cases of: + * - BMG port A/B + * - PTL port B eDP over TypeC PHY */ static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, -- 2.49.1