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From: "Piotr Piórkowski" <piotr.piorkowski@intel.com>
To: Lukasz Laguna <lukasz.laguna@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <michal.wajdeczko@intel.com>
Subject: Re: [PATCH v2 4/4] drm/xe/pf: Handle MERT catastrophic errors
Date: Mon, 24 Nov 2025 14:52:41 +0100	[thread overview]
Message-ID: <20251124135241.7tdfq7lpz54ec4gg@intel.com> (raw)
In-Reply-To: <20251031080501.844-5-lukasz.laguna@intel.com>

Lukasz Laguna <lukasz.laguna@intel.com> wrote on pią [2025-paź-31 09:05:01 +0100]:
> The MERT block triggers an interrupt when a catastrophic error occurs.
> Update the interrupt handler to read the MERT catastrophic error type
> and log appropriate debug message.
> 
> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
> ---
> v2:
>  - rebase,
>  - fix the VF ID extraction from the read value.
> ---
>  drivers/gpu/drm/xe/regs/xe_mert_regs.h |  5 +++++
>  drivers/gpu/drm/xe/xe_mert.c           | 11 +++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> index aef66c04901d..c345e11ceea8 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
> @@ -10,6 +10,11 @@
>  
>  #define MERT_LMEM_CFG				XE_REG(0x1448b0)
>  
> +#define MERT_TLB_CT_INTR_ERR_ID_PORT		XE_REG(0x145190)
> +#define   MERT_TLB_CT_VFID_MASK			REG_GENMASK(16, 9)
> +#define   MERT_TLB_CT_ERROR_MASK		REG_GENMASK(5, 0)
> +#define     MERT_TLB_CT_LMTT_FAULT		0x05
> +
>  #define MERT_TLB_INV_DESC_A			XE_REG(0x14cf7c)
>  #define   MERT_TLB_INV_DESC_A_VALID		REG_BIT(0)
>  
> diff --git a/drivers/gpu/drm/xe/xe_mert.c b/drivers/gpu/drm/xe/xe_mert.c
> index 304cc8421999..e5e0ad872506 100644
> --- a/drivers/gpu/drm/xe/xe_mert.c
> +++ b/drivers/gpu/drm/xe/xe_mert.c
> @@ -55,10 +55,21 @@ void xe_mert_irq_handler(struct xe_device *xe, u32 master_ctl)
>  	struct xe_tile *tile = xe_device_get_root_tile(xe);
>  	unsigned long flags;
>  	u32 reg_val;
> +	u8 err;
>  
>  	if (!(master_ctl & SOC_H2DMEMINT_IRQ))
>  		return;
>  
> +	reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT);
> +	xe_mmio_write32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT, 0);
> +
> +	err = reg_val & MERT_TLB_CT_ERROR_MASK;

NIT: To be consistent with the rest of the code, I would also use FIELD_GET here.


> +	if (err == MERT_TLB_CT_LMTT_FAULT)
> +		drm_dbg(&xe->drm, "MERT catastrophic error: LMTT fault (VF%u)\n",
> +			FIELD_GET(MERT_TLB_CT_VFID_MASK, reg_val));
> +	else if (err)
> +		drm_dbg(&xe->drm, "MERT catastrophic error: Unexpected fault (0x%x)\n", err);
> +
>  	spin_lock_irqsave(&tile->mert.lock, flags);
>  	if (tile->mert.tlb_inv_triggered) {
>  		reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);

LGTM:
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>

> -- 
> 2.40.0
> 

-- 

  reply	other threads:[~2025-11-24 13:52 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31  8:04 [PATCH v2 0/4] PF: Add support for MERT Lukasz Laguna
2025-10-31  8:04 ` [PATCH v2 1/4] drm/xe: Add device flag to indicate standalone MERT Lukasz Laguna
2025-10-31  8:04 ` [PATCH v2 2/4] drm/xe/pf: Configure LMTT in MERT Lukasz Laguna
2025-11-24 10:47   ` Piotr Piórkowski
2025-10-31  8:05 ` [PATCH v2 3/4] drm/xe/pf: Add TLB invalidation support for MERT Lukasz Laguna
2025-11-24 13:43   ` Piotr Piórkowski
2025-10-31  8:05 ` [PATCH v2 4/4] drm/xe/pf: Handle MERT catastrophic errors Lukasz Laguna
2025-11-24 13:52   ` Piotr Piórkowski [this message]
2025-10-31  8:12 ` ✗ CI.checkpatch: warning for PF: Add support for MERT Patchwork
2025-10-31  8:14 ` ✓ CI.KUnit: success " Patchwork
2025-10-31  9:29 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-31 19:25 ` ✓ Xe.CI.Full: " Patchwork

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