From: Lukasz Laguna <lukasz.laguna@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: michal.wajdeczko@intel.com, piotr.piorkowski@intel.com,
lukasz.laguna@intel.com
Subject: [PATCH v3 4/4] drm/xe/pf: Handle MERT catastrophic errors
Date: Mon, 24 Nov 2025 20:02:37 +0100 [thread overview]
Message-ID: <20251124190237.20503-5-lukasz.laguna@intel.com> (raw)
In-Reply-To: <20251124190237.20503-1-lukasz.laguna@intel.com>
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The MERT block triggers an interrupt when a catastrophic error occurs.
Update the interrupt handler to read the MERT catastrophic error type
and log appropriate debug message.
Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
---
v3:
- use FIELD_GET() for consistency
---
drivers/gpu/drm/xe/regs/xe_mert_regs.h | 5 +++++
drivers/gpu/drm/xe/xe_mert.c | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
index aef66c04901d..c345e11ceea8 100644
--- a/drivers/gpu/drm/xe/regs/xe_mert_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h
@@ -10,6 +10,11 @@
#define MERT_LMEM_CFG XE_REG(0x1448b0)
+#define MERT_TLB_CT_INTR_ERR_ID_PORT XE_REG(0x145190)
+#define MERT_TLB_CT_VFID_MASK REG_GENMASK(16, 9)
+#define MERT_TLB_CT_ERROR_MASK REG_GENMASK(5, 0)
+#define MERT_TLB_CT_LMTT_FAULT 0x05
+
#define MERT_TLB_INV_DESC_A XE_REG(0x14cf7c)
#define MERT_TLB_INV_DESC_A_VALID REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_mert.c b/drivers/gpu/drm/xe/xe_mert.c
index 304cc8421999..f7689e922953 100644
--- a/drivers/gpu/drm/xe/xe_mert.c
+++ b/drivers/gpu/drm/xe/xe_mert.c
@@ -55,10 +55,21 @@ void xe_mert_irq_handler(struct xe_device *xe, u32 master_ctl)
struct xe_tile *tile = xe_device_get_root_tile(xe);
unsigned long flags;
u32 reg_val;
+ u8 err;
if (!(master_ctl & SOC_H2DMEMINT_IRQ))
return;
+ reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT);
+ xe_mmio_write32(&tile->mmio, MERT_TLB_CT_INTR_ERR_ID_PORT, 0);
+
+ err = FIELD_GET(MERT_TLB_CT_ERROR_MASK, reg_val);
+ if (err == MERT_TLB_CT_LMTT_FAULT)
+ drm_dbg(&xe->drm, "MERT catastrophic error: LMTT fault (VF%u)\n",
+ FIELD_GET(MERT_TLB_CT_VFID_MASK, reg_val));
+ else if (err)
+ drm_dbg(&xe->drm, "MERT catastrophic error: Unexpected fault (0x%x)\n", err);
+
spin_lock_irqsave(&tile->mert.lock, flags);
if (tile->mert.tlb_inv_triggered) {
reg_val = xe_mmio_read32(&tile->mmio, MERT_TLB_INV_DESC_A);
--
2.40.0
next prev parent reply other threads:[~2025-11-24 19:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 19:02 [PATCH v3 0/4] PF: Add support for MERT Lukasz Laguna
2025-11-24 19:02 ` [PATCH v3 1/4] drm/xe: Add device flag to indicate standalone MERT Lukasz Laguna
2025-11-24 19:02 ` [PATCH v3 2/4] drm/xe/pf: Configure LMTT in MERT Lukasz Laguna
2025-11-24 19:18 ` Dixit, Ashutosh
2025-11-24 19:26 ` Dixit, Ashutosh
2025-11-25 7:38 ` Piotr Piórkowski
2025-11-24 19:02 ` [PATCH v3 3/4] drm/xe/pf: Add TLB invalidation support for MERT Lukasz Laguna
2025-11-24 19:02 ` Lukasz Laguna [this message]
2025-11-27 10:46 ` [PATCH v3 4/4] drm/xe/pf: Handle MERT catastrophic errors K V P, Satyanarayana
2025-11-27 11:29 ` Laguna, Lukasz
2025-11-25 4:13 ` ✗ CI.checkpatch: warning for PF: Add support for MERT (rev2) Patchwork
2025-11-25 4:15 ` ✓ CI.KUnit: success " Patchwork
2025-11-25 5:27 ` ✓ Xe.CI.BAT: " Patchwork
2025-11-25 8:29 ` ✗ Xe.CI.Full: failure " Patchwork
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