[PATCH 2/4] drm/i915/psr: Perform vblank evasion on async flip as well for PSR

["Jouni Högander" <jouni.hogander@intel.com>]

PSR2_MAN_TRK_CTL[SF Continuous full frame] is sampled on the rising edge of
delayed vblank. SW must ensure this bit is not changing around that. Due to
this PSR2 Selective Fetch needs vblank evasion.

Currently vblank evasion is not done on async flip. Perform it in case
required by PSR.

Bspec: 50424
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 153ff4b4b52c..42c4ce07f8c0 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -433,7 +433,8 @@ static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_sta
 		(intel_crtc_needs_color_update(crtc_state) &&
 		 !HAS_DOUBLE_BUFFERED_LUT(display)) &&
 		!intel_color_uses_dsb(crtc_state) &&
-		!crtc_state->use_dsb;
+		!crtc_state->use_dsb &&
+		!crtc_state->do_async_flip;
 }
 
 static void intel_crtc_vblank_work(struct kthread_work *base)
@@ -539,7 +540,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
 	if (new_crtc_state->do_async_flip) {
 		intel_crtc_prepare_vblank_event(new_crtc_state,
 						&crtc->flip_done_event);
-		return;
+		if (!intel_psr_needs_evasion(new_crtc_state))
+			return;
 	}
 
 	if (intel_crtc_needs_vblank_work(new_crtc_state))
-- 
2.43.0