[PATCH 0/3] drm/xe/xe3p_lpg: L2 flush optimization

[Tejas Upadhyay <tejas.upadhyay@intel.com>]

The optimization involves two key changes:

Hardware-assisted Transient Display Flush: 
The new hardware can automatically manage the flushing of "transient" 
display data from the L2 cache. This eliminates the need for manual 
(software-driven) transient display (TD) flushes by the driver, 
simplifying the code and likely improving efficiency.

Transient Application (App) Cacheline Management: 
The hardware gains the ability to flush transient application cache 
lines more efficiently. The patch handles the necessary integration 
to utilize this new functionality and manages manual flushing where 
it is still required, ensuring data coherency and optimizing 
performance. 

Tejas Upadhyay (3):
  drm/xe/xe3p_lpg: flush userptr/shrinker bo cachelines manually
  drm/xe/xe3p_lpg: Enable L2 flush optimization feature
  drm/xe/xe3p: Skip TD flush

 drivers/gpu/drm/xe/xe_bo.c       |  3 ++-
 drivers/gpu/drm/xe/xe_device.c   | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_device.h   |  1 +
 drivers/gpu/drm/xe/xe_guc.c      |  3 +++
 drivers/gpu/drm/xe/xe_guc_fwif.h |  1 +
 drivers/gpu/drm/xe/xe_userptr.c  |  3 ++-
 6 files changed, 37 insertions(+), 2 deletions(-)

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2.34.1