From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40B9FD116F9 for ; Tue, 2 Dec 2025 06:27:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DEBAF10E559; Tue, 2 Dec 2025 06:27:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OQIBy64c"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE66B10E558; Tue, 2 Dec 2025 06:27:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764656867; x=1796192867; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=U5pT0yQ0tbDn4iEq4D0XD+8Rz/1jIjiI9n/lPgA/rtg=; b=OQIBy64cQU9RjLItVtG29FwXKaB2nwwubSXVK4bcZfQn3y9RQJ9axolQ Q6h9jGW8z+jXxBSTHJ1zIBE3/owfD8mkSh7q8lGvBtkQS53QJulLiV5HY +6Z8AlcX3YVbb94Xc8EAGcGzWRzs+QVPE32+hMdFRoiNdmw2Ve7tYVnZi 9wSC9rmVHHpflOYQs7E2b+EgvY/njZPk14xU6am1zzPyM8LR34cwuzcW+ gt3NgWm5MzFXVGs8OOqnSPQG46gkudO7Jqudr8z8gGlxhtaUpsXZZsk34 Gq6v/Wr5o3ISsO0ry2NoVXisf41MFJe97RRhINq7sCO4zLW460VksJl15 Q==; X-CSE-ConnectionGUID: XfK7HF0+Q/ORhzKA/WjzLQ== X-CSE-MsgGUID: o7rVA/O2S/u/BzB1gjmVUg== X-IronPort-AV: E=McAfee;i="6800,10657,11630"; a="66499932" X-IronPort-AV: E=Sophos;i="6.20,242,1758610800"; d="scan'208";a="66499932" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2025 22:27:46 -0800 X-CSE-ConnectionGUID: GrK0jlhrR/6uix2mm4u/OA== X-CSE-MsgGUID: 49fyHRP1RcW8vftC8iDeRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,242,1758610800"; d="scan'208";a="193961351" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa007.fm.intel.com with ESMTP; 01 Dec 2025 22:27:40 -0800 From: Arun R Murthy Date: Tue, 02 Dec 2025 11:57:05 +0530 Subject: [PATCH [RESEND] v9 11/20] drm/i915/histogram: histogram interrupt handling MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251202-dpst-v9-11-f2abb2ca2465@intel.com> References: <20251202-dpst-v9-0-f2abb2ca2465@intel.com> In-Reply-To: <20251202-dpst-v9-0-f2abb2ca2465@intel.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , Lucas De Marchi , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, suraj.kandpal@intel.com Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Upon enabling histogram an interrupt is triggered after the generation of the statistics. This patch registers the histogram interrupt and handles the interrupt. v2: Added intel_crtc backpointer to intel_histogram struct (Jani) Removed histogram_wq and instead use dev_priv->unodered_eq (Jani) v3: Replaced drm_i915_private with intel_display (Suraj) Refactored the histogram read code (Jani) v4: Rebased after addressing comments on patch 1 v5: removed the retry logic and moved to patch7 (Jani) Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +- drivers/gpu/drm/i915/display/intel_display_regs.h | 5 +- drivers/gpu/drm/i915/display/intel_histogram.c | 108 +++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_histogram.h | 3 + 4 files changed, 117 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 9adeebb376b189ef72a97e0206e0c24b0f4e7117..ad1bf8c75fe1e33271ad054407b8ec1239c76064 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -22,6 +22,7 @@ #include "intel_fdi_regs.h" #include "intel_fifo_underrun.h" #include "intel_gmbus.h" +#include "intel_histogram.h" #include "intel_hotplug_irq.h" #include "intel_parent.h" #include "intel_pipe_crc_regs.h" @@ -1527,6 +1528,9 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) if (iir & GEN8_PIPE_FIFO_UNDERRUN) intel_cpu_fifo_underrun_irq_handler(display, pipe); + if (iir & GEN9_PIPE_HISTOGRAM_EVENT) + intel_histogram_irq_handler(display, pipe); + fault_errors = iir & gen8_de_pipe_fault_mask(display); if (fault_errors) intel_pipe_fault_irq_handler(display, @@ -2315,7 +2319,7 @@ static void icp_irq_postinstall(struct intel_display *display); void gen8_de_irq_postinstall(struct intel_display *display) { u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) | - GEN8_PIPE_CDCLK_CRC_DONE; + GEN8_PIPE_CDCLK_CRC_DONE | GEN9_PIPE_HISTOGRAM_EVENT; u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(display); u32 de_port_enables; diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index c14d3caa73a7a3ffa86beca4b05700481c601899..7affc89fbe22fe8e09a733b16578136e96a3d1ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -799,7 +799,7 @@ #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define PIPE_HISTOGRAM_EVENT_ENABLE REG_BIT(23) #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) @@ -822,7 +822,7 @@ #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) -#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_HISTOGRAM_EVENT_STATUS REG_BIT(7) #define PIPE_A_PSR_STATUS_VLV (1UL << 6) #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) @@ -1255,6 +1255,7 @@ #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ #define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) +#define GEN9_PIPE_HISTOGRAM_EVENT REG_BIT(12) /* skl+ */ #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index 0d14cd88d1869583a3ade8ded9284425ab217d3e..b42edf7dae7c0b8d083dff81c41a7ed4f7938e84 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -21,7 +21,106 @@ #define HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT 300 /* Precision factor for threshold guardband */ #define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000 -#define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04 +#define HISTOGRAM_BIN_READ_RETRY_COUNT 5 + +static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + int index; + u32 dpstbin; + + for (index = 0; index < ARRAY_SIZE(histogram->bin_data); index++) { + dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); + if (!(dpstbin & DPST_BIN_BUSY)) + histogram->bin_data[index] = dpstbin & DPST_BIN_DATA_MASK; + else + return false; + } + return true; +} + +static void intel_histogram_handle_int_work(struct work_struct *work) +{ + struct intel_histogram *histogram = container_of(work, + struct intel_histogram, work.work); + struct intel_crtc *intel_crtc = histogram->crtc; + struct intel_display *display = to_intel_display(intel_crtc); + struct drm_colorop *colorop; + char event[] = "HISTOGRAM=1", pipe_id[21]; + char *histogram_event[] = { event, pipe_id, NULL }; + int retry; + + snprintf(pipe_id, sizeof(pipe_id), + "PIPE=%u", intel_crtc->base.base.id); + + /* + * TODO: PSR to be exited while reading the Histogram data + * Set DPST_CTL Bin Reg function select to TC + * Set DPST_CTL Bin Register Index to 0 + */ + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + for (retry = 0; retry < HISTOGRAM_BIN_READ_RETRY_COUNT; retry++) { + if (intel_histogram_get_data(intel_crtc)) { + u32 *data; + struct drm_histogram *hist; + + data = kzalloc(sizeof(data) * sizeof(histogram->bin_data), GFP_KERNEL); + if (!data) + return; + memcpy(histogram->bin_data, data, sizeof(histogram->bin_data)); + hist = kzalloc(sizeof(*hist), GFP_KERNEL); + if (!hist) + return; + hist->data_ptr = *data; + hist->nr_elements = sizeof(histogram->bin_data); + + colorop = intel_crtc->base.state->color_pipeline; + /* TODO: fill the drm_histogram_config data back this drm_histogram struct */ + drm_property_replace_global_blob(display->drm, + &colorop->state->histogram_data, + sizeof(struct drm_histogram), + hist, &intel_crtc->base.base, + colorop->histogram_data_property); + /* Notify user for Histogram readiness */ + if (kobject_uevent_env(&display->drm->primary->kdev->kobj, + KOBJ_CHANGE, histogram_event)) + drm_err(display->drm, + "Sending HISTOGRAM event failed\n"); + break; + } + } + if (retry >= HISTOGRAM_BIN_READ_RETRY_COUNT) { + drm_err(display->drm, "Histogram bin read failed with max retry\n"); + return; + } + + /* Enable histogram interrupt */ + intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, + DPST_GUARD_HIST_INT_EN); + + /* Clear histogram interrupt by setting histogram interrupt status bit*/ + intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); +} + +void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe) +{ + struct intel_crtc *intel_crtc = + to_intel_crtc(drm_crtc_from_index(display->drm, pipe)); + struct intel_histogram *histogram = intel_crtc->histogram; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + + if (!histogram->enable) { + drm_err(display->drm, + "Spurious interrupt, histogram not enabled\n"); + return; + } + + queue_delayed_work(i915->unordered_wq, + &histogram->work, 0); +} int intel_histogram_atomic_check(struct intel_crtc *intel_crtc) { @@ -73,7 +172,7 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc, u8 mode) DPST_GUARD_THRESHOLD_GB_MASK | DPST_GUARD_INTERRUPT_DELAY_MASK | DPST_GUARD_HIST_INT_EN, DPST_GUARD_THRESHOLD_GB(gbandthreshold) | - DPST_GUARD_INTERRUPT_DELAY(HISTOGRAM_DEFAULT_GUARDBAND_DELAY) | + DPST_GUARD_INTERRUPT_DELAY(0x04) | DPST_GUARD_HIST_INT_EN); /* Clear pending interrupts has to be done on separate write */ @@ -106,6 +205,7 @@ static void intel_histogram_disable(struct intel_crtc *intel_crtc) intel_de_rmw(display, DPST_CTL(pipe), DPST_CTL_IE_HIST_EN, 0); + cancel_delayed_work(&histogram->work); histogram->enable = false; } @@ -131,6 +231,7 @@ void intel_histogram_finish(struct intel_crtc *intel_crtc) { struct intel_histogram *histogram = intel_crtc->histogram; + cancel_delayed_work_sync(&histogram->work); kfree(histogram); } @@ -155,5 +256,8 @@ int intel_histogram_init(struct intel_crtc *crtc) histogram->can_enable = false; histogram->caps = histogram_caps; + INIT_DEFERRABLE_WORK(&histogram->work, + intel_histogram_handle_int_work); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h index 71ca706ebef9873c482f9714f614f6f6cc1eb2f0..bd559d90e9b9fc8f5afdbc31c47702a99569b712 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.h +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -12,6 +12,8 @@ struct drm_property_blob; struct drm_histogram_config; struct drm_histogram_caps; struct intel_crtc; +struct intel_display; +enum pipe; #define HISTOGRAM_BIN_COUNT 32 @@ -37,6 +39,7 @@ enum intel_global_hist_lut { INTEL_HISTOGRAM_PIXEL_FACTOR, }; +void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe); int intel_histogram_atomic_check(struct intel_crtc *intel_crtc); int intel_histogram_update(struct intel_crtc *intel_crtc, struct drm_histogram_config *config); -- 2.25.1