From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6C7FD116F5 for ; Tue, 2 Dec 2025 06:28:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 74A4410E580; Tue, 2 Dec 2025 06:28:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EGPOkBaC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 72ADE10E576; Tue, 2 Dec 2025 06:28:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764656910; x=1796192910; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=eptpgrqEeKqmwLImiXdOEDGmU4R9xsmeWyQQ26WQR30=; b=EGPOkBaCK/VLYn2/CR0NqXC2bsHkogZKPvQbCxFPym14m8tKJX89LUtK x/2rCu32bIJfcR1+3K8u20veHjNQVcOlcqjmh07fwYGy3BNViPVA80LYK DDz4H0n35iPKD+bAq6km2XeDmAJ3n8IMa0wfssvcWIcjeDRuGOdF0o1KI 2gC1LSYx+Buht9NgtoHmz065PlJVogOISIGXOBnj5+GAMq7tfoU3geksv PyKVFYf6FC1bBwIwCBt/GUik3jtm3fmNpdQpYCnTE629jK5Z6cKr0a1TC f/7amCf2pHtw/7ZRipjGyFH8JzJv6cAhhRTEdvX9/s6+ktc3W8nHnDuSZ w==; X-CSE-ConnectionGUID: bNooElXPRhKcl4Im0qlIvg== X-CSE-MsgGUID: 8sp4gSozSY+b4jb/QMjBkw== X-IronPort-AV: E=McAfee;i="6800,10657,11630"; a="66500027" X-IronPort-AV: E=Sophos;i="6.20,242,1758610800"; d="scan'208";a="66500027" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2025 22:28:29 -0800 X-CSE-ConnectionGUID: fV1ZN602Rqaki2jMmfLIkA== X-CSE-MsgGUID: //0R2sJWRDmbTVc0CA9vvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,242,1758610800"; d="scan'208";a="193961507" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa007.fm.intel.com with ESMTP; 01 Dec 2025 22:28:23 -0800 From: Arun R Murthy Date: Tue, 02 Dec 2025 11:57:12 +0530 Subject: [PATCH [RESEND] v9 18/20] drm/i915/histogram: histogram delay counter doesn't reset MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251202-dpst-v9-18-f2abb2ca2465@intel.com> References: <20251202-dpst-v9-0-f2abb2ca2465@intel.com> In-Reply-To: <20251202-dpst-v9-0-f2abb2ca2465@intel.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , Lucas De Marchi , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , uma.shankar@intel.com, chaitanya.kumar.borah@intel.com, suraj.kandpal@intel.com Cc: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" The delay counter for histogram does not reset and as a result the histogram bin never gets updated. Workaround would be to use save and restore histogram register. v2: Follow the seq in interrupt handler Restore DPST bit 0 read/write dpst ctl rg Restore DPST bit 1 and Guardband Delay Interrupt counter = 0 (Suraj) v3: updated wa version for display 13 and 14 Wa: 14014889975 Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_histogram.c | 14 ++++++++++++++ drivers/gpu/drm/i915/display/intel_histogram_regs.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index cf8aa7b04c4461629b071e49601a0e60d7609a08..2dfc07878ababc11c88468645eae5a58be3b1ee8 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -55,6 +55,11 @@ static void intel_histogram_handle_int_work(struct work_struct *work) snprintf(pipe_id, sizeof(pipe_id), "PIPE=%u", intel_crtc->base.base.id); + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 13, 14)) + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_RESTORE, 0); + /* * TODO: PSR to be exited while reading the Histogram data * Set DPST_CTL Bin Reg function select to TC @@ -97,6 +102,15 @@ static void intel_histogram_handle_int_work(struct work_struct *work) return; } + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 13, 14)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT | + DPST_CTL_RESTORE, + DPST_CTL_GUARDBAND_INTERRUPT_DELAY(0x0) | + DPST_CTL_RESTORE); + /* Enable histogram interrupt */ intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, DPST_GUARD_HIST_INT_EN); diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index 71daf5ac2dd9ac987b256a35161b3b6977992e95..73d2de05ebe777ca7141eee01ec8ce09b53ee5c8 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -14,6 +14,8 @@ #define DPST_CTL_RESTORE REG_BIT(28) #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) #define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT REG_GENMASK(23, 16) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY(val) REG_FIELD_PREP(DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT, val) #define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) #define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) -- 2.25.1