From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 229A1D116F5 for ; Tue, 2 Dec 2025 07:36:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D066410E576; Tue, 2 Dec 2025 07:36:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G7vohKga"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9014410E576; Tue, 2 Dec 2025 07:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764661008; x=1796197008; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GFgCFYAyZJIMw7aJ3fhHyo2QSldyZDNWAhHAhAloa3s=; b=G7vohKga2wJMObVhQz6tTXdcZql6I9PkNgWQB1nLL0j6aoNvk6jjCf8D JebVgIhp3f3Fa5G2YnRHDmM9jKc7p1hKTLLTVYTpMCY9P+6xKGU3Cxiti UVqHMOVXgKj3CN05LPmBWlFfWlOL5AHxAB3k7L1oQbxyoM2reVoU9LxAL /6VqAG5E9EAc/KxknPN0ovC+V0fN0WdpADLnD4lszK+3D9ccbTfKX1XzP RjOi40GgNkzCVNRc+aXXDhwEbJXnxsQCGOe6b2XX1DpUoLC9r8eOQ0Oci gYoeX2Cl0fD+ieQ7dzxHQYAWCpysbARxNd6DzeEjoHs7WGWmN76ZjZFnU w==; X-CSE-ConnectionGUID: AoAmEEExTFOJaNCInA4t8w== X-CSE-MsgGUID: qDBvo2QvSduWCqENlGwVWA== X-IronPort-AV: E=McAfee;i="6800,10657,11630"; a="84219208" X-IronPort-AV: E=Sophos;i="6.20,242,1758610800"; d="scan'208";a="84219208" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2025 23:36:48 -0800 X-CSE-ConnectionGUID: f9ITZGv0TiSxaryQ8jcSmw== X-CSE-MsgGUID: Mc0ObqVYSZ2wD0qbZzwKBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,242,1758610800"; d="scan'208";a="198504780" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa003.jf.intel.com with ESMTP; 01 Dec 2025 23:36:46 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, mitulkumar.ajitkumar.golani@intel.com, ankit.k.nautiyal@intel.com, ville.syrjala@linux.intel.com, uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v10 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Date: Tue, 2 Dec 2025 13:06:39 +0530 Message-ID: <20251202073659.926838-5-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251202073659.926838-1-mitulkumar.ajitkumar.golani@intel.com> References: <20251202073659.926838-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Ville Syrjälä Calculate delayed vblank start position with the help of added vmin/vmax stuff for next frame and final computation. --v2: - Correct Author details. --v3: - Separate register details from this patch. --v4: - Add mask macros. --v5: - As live prefix params indicate timings for current frame, read just _live prefix values instead of next frame timings as done previously. - Squash Refactor vrr params patch. --v6: - Use error code while returning invalid values. (Jani, Nikula) Signed-off-by: Ville Syrjälä Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 5 +++ 2 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index b92c42fde937..31f3a7b6e00d 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state, return value - crtc_state->set_context_latency; } +static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state, + int vmin_vmax) +{ + return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband; +} + /* * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to * Vtotal value. @@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state) return intel_vrr_vmin_vblank_start(crtc_state) - crtc_state->set_context_latency; } + +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp = 0; + + tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder)); + + if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0) + return -EINVAL; + + return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1); +} + +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp = 0; + + tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder)); + + if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0) + return -EINVAL; + + return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1); +} + +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp = 0; + + tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder)); + + return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1); +} + +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp = 0; + + tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder)); + + return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index bc9044621635..66fb9ad846f2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display); int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state); + #endif /* __INTEL_VRR_H__ */ -- 2.48.1