From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Subject: [PATCH 2/3] drm/xe/rtp: Whitelist OAMERT MMIO trigger registers
Date: Fri, 5 Dec 2025 13:26:12 -0800 [thread overview]
Message-ID: <20251205212613.826224-3-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20251205212613.826224-1-ashutosh.dixit@intel.com>
Whitelist OAMERT registers to enable userspace to execute MMIO triggers on
OAMERT units. Registers are whitelisted for compute and copy class engines.
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/xe/xe_reg_whitelist.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index da49c69076a47..1391cb6ec9c62 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -9,6 +9,7 @@
#include "regs/xe_gt_regs.h"
#include "regs/xe_oa_regs.h"
#include "regs/xe_regs.h"
+#include "xe_device.h"
#include "xe_gt_types.h"
#include "xe_gt_printk.h"
#include "xe_platform_types.h"
@@ -26,6 +27,13 @@ static bool match_not_render(const struct xe_device *xe,
return hwe->class != XE_ENGINE_CLASS_RENDER;
}
+static bool match_has_mert(const struct xe_device *xe,
+ const struct xe_gt *gt,
+ const struct xe_hw_engine *hwe)
+{
+ return xe_device_has_mert((struct xe_device *)xe);
+}
+
static const struct xe_rtp_entry_sr register_whitelist[] = {
{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
@@ -94,6 +102,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
OAM_STATUS(XE_OAM_SCMI_1_BASE_ADJ), \
OAM_HEAD_POINTER(XE_OAM_SCMI_1_BASE_ADJ))
+#define WHITELIST_OA_MERT_MMIO_TRG \
+ WHITELIST_OA_MMIO_TRG(OAMERT_MMIO_TRG, OAMERT_STATUS, OAMERT_HEAD_POINTER)
+
{ XE_RTP_NAME("oag_mmio_trg_rcs"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
ENGINE_CLASS(RENDER)),
@@ -114,6 +125,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
ENGINE_CLASS(VIDEO_ENHANCE)),
XE_RTP_ACTIONS(WHITELIST_OAM_MMIO_TRG)
},
+ { XE_RTP_NAME("oa_mert_mmio_trg_ccs"),
+ XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COMPUTE)),
+ XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
+ },
+ { XE_RTP_NAME("oa_mert_mmio_trg_bcs"),
+ XE_RTP_RULES(FUNC(match_has_mert), ENGINE_CLASS(COPY)),
+ XE_RTP_ACTIONS(WHITELIST_OA_MERT_MMIO_TRG)
+ },
};
static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
--
2.48.1
next prev parent reply other threads:[~2025-12-05 21:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-05 21:26 [PATCH 0/3] drm/xe/oa: Expose MERT OA unit Ashutosh Dixit
2025-12-05 21:26 ` [PATCH 1/3] drm/xe/oa/uapi: " Ashutosh Dixit
2025-12-08 12:48 ` Rodrigo Vivi
2025-12-08 19:10 ` Dixit, Ashutosh
2025-12-08 19:53 ` Rodrigo Vivi
2025-12-15 19:34 ` Dixit, Ashutosh
2025-12-17 1:12 ` Dixit, Ashutosh
2025-12-17 22:36 ` Rodrigo Vivi
2025-12-05 21:26 ` Ashutosh Dixit [this message]
2025-12-05 23:34 ` [PATCH 2/3] drm/xe/rtp: Whitelist OAMERT MMIO trigger registers Umesh Nerlige Ramappa
2025-12-05 21:26 ` [PATCH 3/3] drm/xe/oa: Always set OAG_OAGLBCTXCTRL_COUNTER_RESUME Ashutosh Dixit
2025-12-05 23:36 ` Umesh Nerlige Ramappa
2025-12-05 23:15 ` ✓ CI.KUnit: success for drm/xe/oa: Expose MERT OA unit Patchwork
2025-12-06 0:27 ` ✓ Xe.CI.BAT: " Patchwork
2025-12-06 12:07 ` ✗ Xe.CI.Full: failure " Patchwork
2025-12-15 19:37 ` [PATCH 0/3] " Dixit, Ashutosh
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