From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E27AD637DC for ; Tue, 16 Dec 2025 21:49:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0420410E9A6; Tue, 16 Dec 2025 21:49:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gVyhw4n0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id B7C5310E06C; Tue, 16 Dec 2025 21:49:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765921766; x=1797457766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t1B4nwXkd8lkBz/YWX1T0zkbHgh5BukCJx4y164mOmI=; b=gVyhw4n0PGNtX7uBbj+WVlPb8kwv9mbaRPTY8SnTFwsjccB2JyJZkA+o HZ/ZE0HMx++sg1Qq5Tpvn8MULmtP9QEl/gUUwHVWAW1rgnrTn6DI7ljWW wAz/vrlbJKPkacHHp8tYpc9lBoc3g+3DfL7q+T4KenrLmmnRS47+vZvRO nx7P4p4P/YI4l8lCDLMSVAqatLv4eUd0s3yadCUZTjm6dZqe6CWsTMkuN dQUUyaLa8cxmTv5BQvxcPmWfurTOdJJCTCOyHFlSKP55uK3Y50sJutxUc 50C3gDZ7DuBtCh0eQNdJXFVf1x8ItQl8V7fBvEFTOS8EyTQfgoiaX/+Cy g==; X-CSE-ConnectionGUID: vXU6tnPxQ0ebEOU5jLxqZQ== X-CSE-MsgGUID: 2lPM9VufQ46KFb6gMai3cg== X-IronPort-AV: E=McAfee;i="6800,10657,11644"; a="67045825" X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="67045825" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 13:49:26 -0800 X-CSE-ConnectionGUID: locRs7EfSn6whCoOrHSaGA== X-CSE-MsgGUID: QlZShiNYSQC/myHhlpPYTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,154,1763452800"; d="scan'208";a="198615365" Received: from mrbroom-desk1.ger.corp.intel.com (HELO mwajdecz-hp.clients.intel.com) ([10.246.20.17]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2025 13:49:24 -0800 From: Michal Wajdeczko To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Daniele Ceraolo Spurio , Michal Wajdeczko , Matthew Brost Subject: [PATCH v3 4/4] drm/xe/pf: Add handling for MLRC adverse event threshold Date: Tue, 16 Dec 2025 22:48:59 +0100 Message-ID: <20251216214902.1429-5-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251216214902.1429-1-michal.wajdeczko@intel.com> References: <20251216214902.1429-1-michal.wajdeczko@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Daniele Ceraolo Spurio Since it is illegal to register a MLRC context when scheduler groups are enabled, the GuC consider the VF doing so as an adverse event. Like for other adverse event, there is a threshold for how many times the event can happen before the GuC throws an error, which we need to add support for. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko Signed-off-by: Michal Wajdeczko Acked-by: Matthew Brost --- drivers/gpu/drm/xe/abi/guc_klvs_abi.h | 9 +++++++++ drivers/gpu/drm/xe/xe_guc_klv_thresholds_set_types.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h index 265a135e7061..89a4f8c504e6 100644 --- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h +++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h @@ -352,6 +352,12 @@ enum { * :1: NORMAL = schedule VF always, irrespective of whether it has work or not * :2: HIGH = schedule VF in the next time-slice after current active * time-slice completes if it has active work + * + * _`GUC_KLV_VF_CFG_THRESHOLD_MULTI_LRC_COUNT` : 0x8A0D + * Given that multi-LRC contexts are incompatible with SRIOV scheduler + * groups and cause the latter to be turned off when registered with the + * GuC, this config allows the PF to set a threshold for multi-LRC context + * registrations by VFs to monitor their behavior. */ #define GUC_KLV_VF_CFG_GGTT_START_KEY 0x0001 @@ -410,6 +416,9 @@ enum { #define GUC_SCHED_PRIORITY_NORMAL 1u #define GUC_SCHED_PRIORITY_HIGH 2u +#define GUC_KLV_VF_CFG_THRESHOLD_MULTI_LRC_COUNT_KEY 0x8a0d +#define GUC_KLV_VF_CFG_THRESHOLD_MULTI_LRC_COUNT_LEN 1u + /* * Workaround keys: */ diff --git a/drivers/gpu/drm/xe/xe_guc_klv_thresholds_set_types.h b/drivers/gpu/drm/xe/xe_guc_klv_thresholds_set_types.h index 5f84da3d10d3..45ab5a3b5218 100644 --- a/drivers/gpu/drm/xe/xe_guc_klv_thresholds_set_types.h +++ b/drivers/gpu/drm/xe/xe_guc_klv_thresholds_set_types.h @@ -37,6 +37,7 @@ define(H2G_STORM, guc_time_us) \ define(IRQ_STORM, irq_time_us) \ define(DOORBELL_STORM, doorbell_time_us) \ + define(MULTI_LRC_COUNT, multi_lrc_count, 70, 53)\ /* end */ /** -- 2.47.1