From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99F2CE8FDB1 for ; Mon, 29 Dec 2025 10:27:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 413FA10E3A5; Mon, 29 Dec 2025 10:27:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fZZD3ZpX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED5A810E3A5; Mon, 29 Dec 2025 10:27:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767004068; x=1798540068; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=o0+lCDVnEnL6GGmH/YQwx+G4sNPtLYjXBXvjoL8hY44=; b=fZZD3ZpXXjsviC5FbkA48E1whtgd2sQ0S8yxW1PLU8KCv8qIgRlMQuom qiOG5NrRvQlOkS1JkOCiIi8BehZuCFDsTWZMKJT4L4KC2YQBYBMdByKCk CyvxrDYo3sEGAWS59q2xMlawIWYF6tmXNw9pHKaQcQC4g2KnAKZ+kkhNm TUrg0WPI4mgM2G0iHwILJSQIX/ImtR07nUwp28uawiryvStLXKmr009Nv ZWl9Uk7l77MPReXKgkrIYVYJOhvIj1B2H8QYfeUhPl8lV2MBazBnZ3P1Z y5VeKNDxzdLGQxw5QCu0iJKOzqw9SjygW9wZ+cSTPnMmc5n4/MyKOhHSP Q==; X-CSE-ConnectionGUID: XZnAXzXiSxGT91hK68Xs7Q== X-CSE-MsgGUID: +qoT6OFGSL2DF6yzaQ+6dQ== X-IronPort-AV: E=McAfee;i="6800,10657,11655"; a="68589308" X-IronPort-AV: E=Sophos;i="6.21,185,1763452800"; d="scan'208";a="68589308" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Dec 2025 02:27:48 -0800 X-CSE-ConnectionGUID: 5XSgbW5nQQSB56Eu8rr00A== X-CSE-MsgGUID: GbUFFY4HRzasfbGycupdBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,185,1763452800"; d="scan'208";a="201350685" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by fmviesa009.fm.intel.com with ESMTP; 29 Dec 2025 02:27:47 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jouni.hogander@intel.com, jani.nikula@intel.com, Animesh Manna Subject: [PATCH v3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling Date: Mon, 29 Dec 2025 15:29:13 +0530 Message-Id: <20251229095913.57790-1-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Unused bandwidth can be used by external display agents for Panel Replay enabled DP panel during idleness with link on. Enable source to replace dummy data from the display with data from another agent by programming TRANS_DP2_CTL [Panel Replay Tunneling Enable]. v2: - Enable pr bw optimization along with panel replay enable. [Jani] v3: - Write TRANS_DP2_CTL once for both bw optimization and panel replay enable. [Jani] Bspec: 68920 Signed-off-by: Animesh Manna --- .../gpu/drm/i915/display/intel_display_regs.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 26 +++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 9e0d853f4b61..b6fc249a9f09 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -2051,6 +2051,7 @@ #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) +#define TRANS_DP2_PR_TUNNELING_ENABLE REG_BIT(26) #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) #define _TRANS_DP2_VFREQHIGH_A 0x600a4 diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 91f4ac86c7ad..4283455d58fb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -44,6 +44,7 @@ #include "intel_dmc.h" #include "intel_dp.h" #include "intel_dp_aux.h" +#include "intel_dp_tunnel.h" #include "intel_dsb.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h" @@ -1018,11 +1019,30 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) return frames_before_su_entry; } +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + u8 val; + + if (DISPLAY_VER(display) < 35) + return false; + + if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) + return false; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_TUNNELING_CAPABILITIES, &val); + if (!(val & DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT)) + return false; + + return true; +} + static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_psr *psr = &intel_dp->psr; enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE; if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { u32 val = psr->su_region_et_enabled ? @@ -1035,12 +1055,14 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) val); } + if (!intel_dp_is_edp(intel_dp) && intel_psr_allow_pr_bw_optimization(intel_dp)) + dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE; + intel_de_rmw(display, PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); - intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, - TRANS_DP2_PANEL_REPLAY_ENABLE); + intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, dp2_ctl_val); } static void hsw_activate_psr2(struct intel_dp *intel_dp) -- 2.29.0