From: Stuart Summers <stuart.summers@intel.com>
Cc: matthew.brost@intel.com, intel-xe@lists.freedesktop.org,
Stuart Summers <stuart.summers@intel.com>
Subject: [PATCH 2/2] drm/xe: Enable ring based TLB invalidation for CI
Date: Wed, 14 Jan 2026 00:04:21 +0000 [thread overview]
Message-ID: <20260114000421.331082-3-stuart.summers@intel.com> (raw)
In-Reply-To: <20260114000421.331082-1-stuart.summers@intel.com>
Do not review - for CI only.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index a2ce9da2e3cb..712ac1995c58 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -96,6 +96,7 @@ static const struct xe_graphics_desc graphics_xelpg = {
.has_asid = 1, \
.has_atomic_enable_pte_bit = 1, \
.has_range_tlb_inval = 1, \
+ .has_ring_tlb_inval = 1, \
.has_usm = 1, \
.has_64bit_timestamp = 1, \
.hw_engine_mask = \
--
2.34.1
next prev parent reply other threads:[~2026-01-14 0:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-14 0:04 [PATCH 0/2] Add feature to force ring-based TLB invalidations Stuart Summers
2026-01-14 0:04 ` [PATCH 1/2] drm/xe: " Stuart Summers
2026-01-14 3:26 ` Matthew Brost
2026-01-14 3:40 ` Matthew Brost
2026-01-14 19:22 ` Summers, Stuart
2026-01-16 0:29 ` Summers, Stuart
2026-01-14 0:04 ` Stuart Summers [this message]
2026-01-14 0:11 ` ✓ CI.KUnit: success for " Patchwork
2026-01-14 0:51 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-14 9:49 ` ✗ Xe.CI.Full: failure " Patchwork
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