[v2 02/19] drm/{i915, xe}: Extract South chicken registers from i915_reg.h to display

Uma Shankar
2026-01-21T23:08:33Z

Extract South Chicken registers from i915_reg.h to display header.
This allows intel_pch_refclk.c not to include i915_reg.h

v2: Drop common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 28 +++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_refclk.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 27 ------------------
3 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9f8fbfb2e115..4759a9600d3f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2864,6 +2864,34 @@ enum skl_power_gate {
#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
#define SFUSE_STRAP_DDID_DETECTED (1 << 0)

+#define SOUTH_CHICKEN1 _MMIO(0xc2000)
+#define FDIA_PHASE_SYNC_SHIFT_OVR 19
+#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDIE_HPD REG_BIT(28)
+#define INVERT_DDID_HPD_MTP REG_BIT(27)
+#define INVERT_TC4_HPD REG_BIT(26)
+#define INVERT_TC3_HPD REG_BIT(25)
+#define INVERT_TC2_HPD REG_BIT(24)
+#define INVERT_TC1_HPD REG_BIT(23)
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
+#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define FDI_BC_BIFURCATION_SELECT (1 << 12)
+#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
+#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
+#define SBCLK_RUN_REFCLK_DIS (1 << 7)
+#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
+#define SPT_PWM_GRANULARITY (1 << 0)
+
+#define SOUTH_CHICKEN2 _MMIO(0xc2004)
+#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
+#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
+#define LPT_PWM_GRANULARITY (1 << 5)
+#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
+
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9a89bb6dcf65..5f88663ef5e8 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -5,7 +5,6 @@

#include <drm/drm_print.h>

-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d247e107f42f..80ea0df40b1e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1022,33 +1022,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)

-#define SOUTH_CHICKEN1 _MMIO(0xc2000)
-#define FDIA_PHASE_SYNC_SHIFT_OVR 19
-#define FDIA_PHASE_SYNC_SHIFT_EN 18
-#define INVERT_DDIE_HPD REG_BIT(28)
-#define INVERT_DDID_HPD_MTP REG_BIT(27)
-#define INVERT_TC4_HPD REG_BIT(26)
-#define INVERT_TC3_HPD REG_BIT(25)
-#define INVERT_TC2_HPD REG_BIT(24)
-#define INVERT_TC1_HPD REG_BIT(23)
-#define INVERT_DDID_HPD (1 << 18)
-#define INVERT_DDIC_HPD (1 << 17)
-#define INVERT_DDIB_HPD (1 << 16)
-#define INVERT_DDIA_HPD (1 << 15)
-#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
-#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
-#define FDI_BC_BIFURCATION_SELECT (1 << 12)
-#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
-#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
-#define SBCLK_RUN_REFCLK_DIS (1 << 7)
-#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
-#define SPT_PWM_GRANULARITY (1 << 0)
-#define SOUTH_CHICKEN2 _MMIO(0xc2004)
-#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
-#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
-#define LPT_PWM_GRANULARITY (1 << 5)
-#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
-
#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
--
2.50.1