RE: [v2 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c

Shankar, Uma
2026-01-23T10:49:13Z

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, January 22, 2026 5:44 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v2 15/19] drm/{i915, xe}: Remove i915_reg.h from
> intel_fifo_underrun.c
>
> On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
> > free from including i915_reg.h.
>
> I think these should be in a display register header, not the common one. The
> users are display and gvt, apart from a single use in
> gt_record_global_regs() which should be moved to display. I can send a patch for
> that.

Thanks for sending the change Jani. I will fix this.

Regards,
Uma Shankar

> BR,
> Jani.
>
>
>
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > .../drm/i915/display/intel_fifo_underrun.c | 2 +-
> > drivers/gpu/drm/i915/i915_reg.h | 23 -------------------
> > include/drm/intel/intel_gmd_common_regs.h | 23 +++++++++++++++++++
> > 3 files changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > index b413b3e871d8..c834be759e40 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> > @@ -28,8 +28,8 @@
> > #include <linux/seq_buf.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_irq.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 62d58d7cfa7a..0af2c9c8dc0f
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -326,29 +326,6 @@
> > #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
> > #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
> >
> > -#define GEN7_ERR_INT _MMIO(0x44040)
> > -#define ERR_INT_POISON (1 << 31)
> > -#define ERR_INT_INVALID_GTT_PTE (1 << 29)
> > -#define ERR_INT_INVALID_PTE_DATA (1 << 28)
> > -#define ERR_INT_SPRITE_C_FAULT (1 << 23)
> > -#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
> > -#define ERR_INT_CURSOR_C_FAULT (1 << 21)
> > -#define ERR_INT_SPRITE_B_FAULT (1 << 20)
> > -#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
> > -#define ERR_INT_CURSOR_B_FAULT (1 << 18)
> > -#define ERR_INT_SPRITE_A_FAULT (1 << 17)
> > -#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
> > -#define ERR_INT_CURSOR_A_FAULT (1 << 15)
> > -#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
> > -#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
> > -#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
> > -#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
> > -#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
> > -#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
> > -#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
> > -#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
> > -#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
> > -
> > #define FPGA_DBG _MMIO(0x42300)
> > #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
> >
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > index 049349c365e3..2b2a7f21529a 100644
> > --- a/include/drm/intel/intel_gmd_common_regs.h
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -169,4 +169,27 @@
> > #define INSTPM_TLB_INVALIDATE (1 << 9)
> > #define INSTPM_SYNC_FLUSH (1 << 5)
> >
> > +#define GEN7_ERR_INT _MMIO(0x44040)
> > +#define ERR_INT_POISON (1 << 31)
> > +#define ERR_INT_INVALID_GTT_PTE (1 << 29)
> > +#define ERR_INT_INVALID_PTE_DATA (1 << 28)
> > +#define ERR_INT_SPRITE_C_FAULT (1 << 23)
> > +#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
> > +#define ERR_INT_CURSOR_C_FAULT (1 << 21)
> > +#define ERR_INT_SPRITE_B_FAULT (1 << 20)
> > +#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
> > +#define ERR_INT_CURSOR_B_FAULT (1 << 18)
> > +#define ERR_INT_SPRITE_A_FAULT (1 << 17)
> > +#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
> > +#define ERR_INT_CURSOR_A_FAULT (1 << 15)
> > +#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
> > +#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
> > +#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
> > +#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
> > +#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
> > +#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
> > +#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
> > +#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
> > +#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
> > +
> > #endif
>
> --
> Jani Nikula, Intel