Re: [v2 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c

Jani Nikula
2026-01-22T12:21:11Z

On Thu, 22 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN9_CLKGATE_DIS_0 reg to display header to make
> intel_modeset_setup.c free from i915_reg.h include.
>
> v2: Remove from gmd common header and use display_regs.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
> drivers/gpu/drm/i915/display/intel_display_regs.h | 13 +++++++++++++
> drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
> drivers/gpu/drm/i915/i915_reg.h | 13 -------------
> 3 files changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 1def3dccdf61..ec18ad9a262c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -377,6 +377,19 @@
> #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
> #define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
>
> +/*
> + * GEN9 clock gating regs
> + */
> +#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> +#define DARBF_GATING_DIS REG_BIT(27)
> +#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
> +#define PWM2_GATING_DIS REG_BIT(14)
> +#define PWM1_GATING_DIS REG_BIT(13)
> +
> +#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
> +#define TGL_VRH_GATING_DIS REG_BIT(31)
> +#define DPT_GATING_DIS REG_BIT(22)
> +
> #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
> #define BXT_GMBUS_GATING_DIS (1 << 14)
> #define DG2_DPFC_GATING_DIS REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index d10cbf69a5f8..9b0becee221c 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -11,7 +11,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_vblank.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "intel_atomic.h"
> #include "intel_bw.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c68a64bc7646..86035f54ae7a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -629,19 +629,6 @@
> #define VLV_CLK_CTL2 _MMIO(0x101104)
> #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
>
> -/*
> - * GEN9 clock gating regs
> - */
> -#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> -#define DARBF_GATING_DIS REG_BIT(27)
> -#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
> -#define PWM2_GATING_DIS REG_BIT(14)
> -#define PWM1_GATING_DIS REG_BIT(13)
> -
> -#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
> -#define TGL_VRH_GATING_DIS REG_BIT(31)
> -#define DPT_GATING_DIS REG_BIT(22)
> -
> #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
> #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
> #define PIPEB_HLINE_INT_EN REG_BIT(28)

--
Jani Nikula, Intel