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Ruhl" To: platform-driver-x86@vger.kernel.org, intel-xe@lists.freedesktop.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com Cc: "Michael J. Ruhl" Subject: [PATCH 3/5] drm/xe/vsec: Support Crescent Island PMT Date: Tue, 27 Jan 2026 13:24:22 -0500 Message-ID: <20260127182418.640701-10-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260127182418.640701-7-michael.j.ruhl@intel.com> References: <20260127182418.640701-7-michael.j.ruhl@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Crescent Island (CRI) supports PMT telemetry and crashlog. Add Crescent Island (CRI) discovery structure (DVSEC) information to allow for Xe registration. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/regs/xe_pmt.h | 5 ++++ drivers/gpu/drm/xe/xe_vsec.c | 43 ++++++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h index 240d57993ea6..874f44b79780 100644 --- a/drivers/gpu/drm/xe/regs/xe_pmt.h +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h @@ -18,6 +18,11 @@ #define BMG_TELEMETRY_BASE_OFFSET 0xE0000 #define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE_OFFSET) +#define CRI_TELEMETRY_BASE_OFFSET 0xE0000 +/* for CRI discovery and telemetry are in an indexed window */ +#define CRI_DISCOVERY_OFFSET (SOC_BASE + CRI_TELEMETRY_BASE_OFFSET) +#define CRI_TELEMETRY_OFFSET (SOC_BASE + CRI_TELEMETRY_BASE_OFFSET) + #define BMG_MODS_RESIDENCY_OFFSET (0x4D0) #define BMG_G2_RESIDENCY_OFFSET (0x530) #define BMG_G6_RESIDENCY_OFFSET (0x538) diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c index 44607f1eaa88..254f7ebca6eb 100644 --- a/drivers/gpu/drm/xe/xe_vsec.c +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -19,8 +19,16 @@ #include "regs/xe_pmt.h" -/* PMT GUID value for BMG devices. NOTE: this is NOT a PCI id */ +/* PMT GUID value for BMG and CRI devices. NOTE: this is NOT a PCI id */ #define BMG_DEVICE_ID 0xE2F8 +#define CRI_DEVICE_ID 0xE2F9 + +/* + * sizeof(Crashlog Type1 Version2) = 0x18 (24) bytes + * For BMG and CRI crashlogs are consecutive and start at 0x60. + */ +#define PUNIT_DISC_OFFSET 0x60 +#define OOBMSM_DISC_OFFSET (PUNIT_DISC_OFFSET + 0x18) static struct intel_vsec_header bmg_telemetry = { .rev = 1, @@ -39,7 +47,7 @@ static struct intel_vsec_header bmg_crashlog = { .num_entries = 2, .entry_size = 6, .tbir = 0, - .offset = BMG_DISCOVERY_OFFSET + 0x60, + .offset = BMG_DISCOVERY_OFFSET + PUNIT_DISC_OFFSET, }; static struct intel_vsec_header *bmg_capabilities[] = { @@ -48,9 +56,36 @@ static struct intel_vsec_header *bmg_capabilities[] = { NULL }; +static struct intel_vsec_header cri_telemetry = { + .rev = 1, + .length = 0x10, + .id = VSEC_ID_TELEMETRY, + .num_entries = 3, + .entry_size = 4, + .tbir = 0, + .offset = CRI_DISCOVERY_OFFSET, +}; + +static struct intel_vsec_header cri_crashlog = { + .rev = 1, + .length = 0x10, + .id = VSEC_ID_CRASHLOG, + .num_entries = 2, + .entry_size = 6, + .tbir = 0, + .offset = CRI_DISCOVERY_OFFSET + PUNIT_DISC_OFFSET, +}; + +static struct intel_vsec_header *cri_capabilities[] = { + &cri_telemetry, + &cri_crashlog, + NULL +}; + enum xe_vsec { XE_VSEC_UNKNOWN = 0, XE_VSEC_BMG, + XE_VSEC_CRI, }; static struct intel_vsec_platform_info xe_vsec_info[] = { @@ -58,6 +93,10 @@ static struct intel_vsec_platform_info xe_vsec_info[] = { .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG, .headers = bmg_capabilities, }, + [XE_VSEC_CRI] = { + .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG, + .headers = cri_capabilities, + }, { } }; -- 2.52.0