From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67648D61010 for ; Thu, 29 Jan 2026 12:10:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 241CC10E244; Thu, 29 Jan 2026 12:10:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JbnDtZaB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4B31F10E84A for ; Thu, 29 Jan 2026 12:10:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769688656; x=1801224656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jT5A66TwxtBWedX1V5NxmT6ZIf9befRjTVAsqtJHlzk=; b=JbnDtZaBjNZZoPvRD+5L6R/r6xgiyaP2ySYDVF9oZm8hUIDfL2PQwBX9 80n8xBWFAh6WrJqxzo5mmRstCUaaN+2snl9UWNzODR6w78u1kS/Q5KLYC 2EvP2WIgi05jD9TcMjz9P5Y2xCkDN6tWHklDeD7d9cWVsMn1ZVIddBuW+ 7b0UOjN1wnY9fCiAeUWu3bYFirarNDLVgJpSQMziFLgVQMZ7yVevq++zX BQCNw0Gvh9iTYFSD9bQwqoytcmdCBR7L4Y9etgcTaUwr+r1RAJlVayRq9 xeM2vewkmm7PP4wSHuMiMErav9yZWPHtpC7HNA/VnKUr4hM/Le4uwd8wW w==; X-CSE-ConnectionGUID: CO8mRLWjQPma6a11rVzfPg== X-CSE-MsgGUID: TQ38EazSSL6Xt4LNBhTMxg== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="70964056" X-IronPort-AV: E=Sophos;i="6.21,260,1763452800"; d="scan'208";a="70964056" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 04:10:55 -0800 X-CSE-ConnectionGUID: oY9/76SlRHyUvlE7tj86Tg== X-CSE-MsgGUID: BRlc+uUYQKyfNfim4Y2QrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,260,1763452800"; d="scan'208";a="213062062" Received: from anoopcvi-vm.gar.corp.intel.com ([10.109.80.88]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 04:10:51 -0800 From: "Anoop, Vijay" To: intel-xe@lists.freedesktop.org Cc: umesh.nerlige.ramappa@intel.com, badal.nilawar@intel.com, rodrigo.vivi@intel.com, aravind.iddamsetty@intel.com, riana.tauro@intel.com, anshuman.gupta@intel.com, matthew.d.roper@intel.com, michael.j.ruhl@intel.com, paul.e.luse@intel.com, mohamed.mansoor.v@intel.com, kam.nasim@intel.com, anoop.c.vijay@intel.com Subject: [PATCH v7 1/6] drm/xe/sysctrl: Add System Controller register definitions Date: Thu, 29 Jan 2026 04:10:42 -0800 Message-ID: <20260129121044.3670780-9-anoop.c.vijay@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129121044.3670780-8-anoop.c.vijay@intel.com> References: <20260129121044.3670780-8-anoop.c.vijay@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" From: Anoop Vijay Add register definitions for System Controller mailbox interface on Xe3p dGPU platforms. Signed-off-by: Anoop Vijay --- v4: (Matt) - Use lowercase hex values - Align macro definitions to column 49 - Change to relative register offsets v6: (Matt) - Move protocol constants to xe_sysctrl_mailbox_types.h - Add SYSCTRL_MB_CTRL_MKHI_CMD helper macro --- drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h new file mode 100644 index 000000000000..2e91febfa9a2 --- /dev/null +++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ + +#ifndef _XE_SYSCTRL_REGS_H_ +#define _XE_SYSCTRL_REGS_H_ + +#include "xe_regs.h" + +#define SYSCTRL_BASE_OFFSET 0xdb000 +#define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET) +#define SYSCTRL_MAILBOX_INDEX 0x03 +#define SYSCTRL_BAR_LENGTH 0x1000 + +#define SYSCTRL_MB_CTRL XE_REG(0x10) +#define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31) +#define SYSCTRL_MB_CTRL_IRQ REG_BIT(30) +#define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29) +#define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24) +#define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16) +#define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8) +#define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0) +#define SYSCTRL_MB_CTRL_MKHI_CMD REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5) + +#define SYSCTRL_MB_DATA0 XE_REG(0x14) +#define SYSCTRL_MB_DATA1 XE_REG(0x18) +#define SYSCTRL_MB_DATA2 XE_REG(0x1C) +#define SYSCTRL_MB_DATA3 XE_REG(0x20) + +#define MKHI_FRAME_PHASE REG_BIT(24) +#define MKHI_FRAME_CURRENT_MASK REG_GENMASK(21, 16) +#define MKHI_FRAME_TOTAL_MASK REG_GENMASK(13, 8) +#define MKHI_FRAME_COMMAND_MASK REG_GENMASK(7, 0) + +#endif /* _XE_SYSCTRL_REGS_H_ */ -- 2.43.0