From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 652A7D49C76 for ; Fri, 30 Jan 2026 08:34:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F8B010E92D; Fri, 30 Jan 2026 08:34:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="noLUEQN6"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 450AB10E92D; Fri, 30 Jan 2026 08:33:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769762040; x=1801298040; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RYpyM7n++mB8Xh0QYISTrRAQme0Bqnj3Y8umDSkXH8s=; b=noLUEQN6LKUka4ZX7zwrHc+xoZUA/MNWFtxNY6TqAwuZxD0c+tX6e/PM s70fCriFw9Bp2KMIpyDWG0qZbkZJSEpvtHwzVcuBIDt/WVy36Zm7MCA4y P557+9bQOIoa6dATOcfKeAtqsZs+QG3ho2/A069GRuHbeGPJdNTo8Knk1 Yv9YX/qmge0ydFl+XiuJgTGcN6SmoOFclgXM6JZaLttNsW3ZDusW6E/nr XuWtU1i7G+xJ0AOS1/B5QV5+6yLTO93Dq94MflYX10idvuuHe/YFXxSs5 jSMBJy+8L+TMzAPcnDDCQat9WIrvJezif/mQq1OsI/HqDNIg0Sz11Q9PD Q==; X-CSE-ConnectionGUID: G2PDNrh1Thegm69PACvxiw== X-CSE-MsgGUID: cuJmITSkTDiSxsM1ukl6KA== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="74636597" X-IronPort-AV: E=Sophos;i="6.21,262,1763452800"; d="scan'208";a="74636597" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 00:33:59 -0800 X-CSE-ConnectionGUID: jihr4p5nR1GzQ6sSuPqenA== X-CSE-MsgGUID: ArnraOIWSIurWAkivFLsLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,262,1763452800"; d="scan'208";a="208910003" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 00:33:58 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, imre.deak@intel.com, Ankit Nautiyal Subject: [PATCH 00/17] Account for DSC bubble overhead for horizontal slices Date: Fri, 30 Jan 2026 13:47:55 +0530 Message-ID: <20260130081812.32087-1-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" When DSC is enabled on a pipe, the pipe pixel rate input to cdclk frequency and pipe joiner calculations needs to be adjusted to account for compression overhead: specifically, the "bubbles" added at each horizontal slice boundary. This overhead has always existed, even on earlier platforms, but was not previously accounted for. Currently, the number of joined pipes is computed much earlier than the decision to use DSC: both during the mode_valid phase for each mode and in the compute_config phase for a given mode. As a result, the DSC bubble overhead cannot be considered when determining the number of pipes to join, which may lead to incorrect configurations. This series refactors the sequence of steps used to determine the number of pipes to be joined and the DSC policy. The first few patches restructure the mode_valid and compute config logic to make room for DSC bubble overhead accounting. With these, we iterate over joiner candidates and select the minimal joiner configuration that satisfies the mode-requirements. The later patches introduce the actual overhead adjustment and use it for: the minimum cdclk requirements with DSC, SST mode_valid logic, and SST/MST compute_config logic. Rev 2: - Refactor joiner computation for compute config. - Refactor DSC BW calculation. - Add overhead for SST/MST compute config phase for recomputing joiner requirements for DSC. - NOTE: - For Patch#7 (drm/i915/dp: Rework pipe joiner logic in mode_valid) git diff = --patience is used for better readability. Rev 3: - Use diff = --patience in format-patch for better readability. - Add a macro to iterate over the joiner candidates. - Add a separate helper to check pixel rate against dotclock limit. - Add patch from Chaitanya for additional platform specific limitations [1]. [1] https://patchwork.freedesktop.org/patch/661952/?series=151047&rev=1 Rev 4: - Address review comments from Jani and Imre. - Drop enum for joiner candidates and iterate over num of pipes joined. - Rename some of the helpers. - Split the patch to check for pixel limit for max uncompressed dotclock into PTL and other platforms. For PTL the bspec and HSDES matches, but for other platforms need to confirm the need for the limits. Rev 5: - Address comments from Imre. - Add a patch to remove joiner helpers that are no longer required. - Dropped the patch to replace the joiner loops with an iterator; will follow up this separately. - Modified the patch to enforce pixel limit for max uncomprssed dotclock for pre PTL platforms, and added the limit only for WCL. Limits for prior platforms is intentionally left to avoid regression on these platforms and deal with them if there are actual issues reported. - Use diff = --histogram as its seen to work better for this series as also suggested by Imre. Rev 6: - Address comments from Imre. - Re-add the patch to replace the joiner loops with iterator; [credits to Imre to figure it out and for the suggested changes.] Ankit Nautiyal (15): drm/i915/dp: Early reject bad hdisplay in intel_dp_mode_valid drm/i915/dp: Move num_joined_pipes and related checks together drm/i915/dp: Extract helper to get the hdisplay limit drm/i915/dp: Rework pipe joiner logic in mode_valid drm/i915/dp: Rework pipe joiner logic in compute_config drm/i915/dp_mst: Move the check for dotclock at the end drm/i915/dp_mst: Move the joiner dependent code together drm/i915/dp_mst: Rework pipe joiner logic in mode_valid drm/i915/dp_mst: Extract helper to compute link for given joiner config drm/i915/dp_mst: Rework pipe joiner logic in compute_config drm/i915/dp: Remove unused joiner helpers drm/i915/dp: Introduce helper to check pixel rate against dotclock limits drm/i915/dp: Refactor dsc_slice_count handling in intel_dp_mode_valid() drm/i915/dp: Account for DSC slice overhead drm/i915/dp: Add helpers for joiner candidate loops Chaitanya Kumar Borah (2): drm/i915/display: Add upper limit check for pixel clock drm/i915/display: Extend the max dotclock limit to WCL drivers/gpu/drm/i915/display/intel_display.c | 19 ++ drivers/gpu/drm/i915/display/intel_display.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 312 ++++++++++++------- drivers/gpu/drm/i915/display/intel_dp.h | 19 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 186 +++++++---- drivers/gpu/drm/i915/display/intel_vdsc.c | 1 - drivers/gpu/drm/i915/display/intel_vdsc.h | 3 + 7 files changed, 367 insertions(+), 174 deletions(-) -- 2.45.2