From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E5B2D49C79 for ; Fri, 30 Jan 2026 08:34:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B1A3610E948; Fri, 30 Jan 2026 08:34:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IGkTfqfx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2373210E930; Fri, 30 Jan 2026 08:34:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769762079; x=1801298079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N+Hi4Cr8nuy79LjNWlymVWuOLLqCe0NTims9Uv/+gPQ=; b=IGkTfqfx0V0iKskPyzNZ4Iz0jh6Jm/7Rviu7fuXmzW3pHrQaYhAABy/D na9xZPonzOTLUYPLLdSp8SisCIQiRAUl18XOc2ljENF47loaVSprYhul0 bIVrkSXKG9kn1daLjEqtR9XSDZwp+WRJC5pisVEIxmsII1U+Jckw2HHfC F/QPa/0UNhgm+xUf6rwXFpcD4CVg9HQ8/Mz1E7pUUtbt9lHEryHS9ARQ6 JLu3aBGXIqbhZgp1sUX1sOAYA7mOTOlNo/nVMk0wHX28T53cciM3o6oTw uLF7jT/PbIqUbbiwK9ToysOtOlyOrmGXRKRcGH7Bp8vIUQbbNbnMHWtWq A==; X-CSE-ConnectionGUID: m5noT7hLTt2Fqi+KVoZwQQ== X-CSE-MsgGUID: GQKXlIo6SiOcVFMegT4Ehw== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="74636688" X-IronPort-AV: E=Sophos;i="6.21,262,1763452800"; d="scan'208";a="74636688" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 00:34:39 -0800 X-CSE-ConnectionGUID: B93M197QRNiXOLni8H1dbA== X-CSE-MsgGUID: G7DUZ6EDSaOfMhgsepqHwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,262,1763452800"; d="scan'208";a="208910133" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 00:34:25 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, imre.deak@intel.com, Ankit Nautiyal Subject: [PATCH 13/17] drm/i915/dp: Refactor dsc_slice_count handling in intel_dp_mode_valid() Date: Fri, 30 Jan 2026 13:48:08 +0530 Message-ID: <20260130081812.32087-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260130081812.32087-1-ankit.k.nautiyal@intel.com> References: <20260130081812.32087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Make dsc_slice_count closer to the block where it is used and promote it from u8 to int. This aligns it with upcoming DSC bubble pixel-rate adjustments, where the slice count participates in wider arithmetic. Currently, for non-eDP (DP/DP_MST) cases the slice count is computed only inside intel_dp_dsc_mode_valid() and is not used by the caller. Once DSC bubble handling is added, dp_mode_valid() will need access to its own local slice count for non-eDP cases as well. Signed-off-by: Ankit Nautiyal Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bf90605ec9cb..61b86cdff3ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1436,7 +1436,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; u16 dsc_max_compressed_bpp = 0; - u8 dsc_slice_count = 0; enum drm_mode_status status; bool dsc = false; int num_joined_pipes; @@ -1486,6 +1485,8 @@ intel_dp_mode_valid(struct drm_connector *_connector, */ status = MODE_CLOCK_HIGH; for (num_joined_pipes = 1; num_joined_pipes <= I915_MAX_PIPES; num_joined_pipes++) { + int dsc_slice_count = 0; + if (connector->force_joined_pipes && num_joined_pipes != connector->force_joined_pipes) continue; @@ -1503,6 +1504,11 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (intel_dp_has_dsc(connector)) { int pipe_bpp; + dsc_slice_count = intel_dp_dsc_get_slice_count(connector, + target_clock, + mode->hdisplay, + num_joined_pipes); + /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked @@ -1517,12 +1523,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, dsc_max_compressed_bpp = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; - dsc_slice_count = - intel_dp_dsc_get_slice_count(connector, - target_clock, - mode->hdisplay, - num_joined_pipes); - dsc = dsc_max_compressed_bpp && dsc_slice_count; } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { unsigned long bw_overhead_flags = 0; -- 2.45.2