From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64B37D49C76 for ; Fri, 30 Jan 2026 08:34:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23B7710E93B; Fri, 30 Jan 2026 08:34:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="V3UvZ4sD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id D553210E946; Fri, 30 Jan 2026 08:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769762085; x=1801298085; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hk1qRDoawFpqOCPOl9nTuUjvr9SSKs9+pMF+ZFkrmB4=; b=V3UvZ4sD/fz+dPCUtQP1BMPMbxz+7RnuwigymKfBw63VtMh5KfUkWy/V kJrBcrQkHs+5dmGcdRPsr1XJH4eIqcqGG4XnI8n5rrDYieZfH5Bad5PCM +VDXL5Fw5gwRh8TcGkf9U2eTzjicsGlWC4PfL5LX/yjxRBZWWKwZhmbeP cF4PIBzo7ORylulC/ZKbMGfYba4y9L5UufDWKG/w/57yEAQVVn6V3ePGW FMfjvqZIspYfFrKhRd6j5YFCYtal801Hc4WjeoEdwgWCbgcm6gPprK6oy Fk23qKmwQhUUt6zAEQ9B1WjqiOGnN/Zr3oTEFIEqLdUpCc+BYCpTNh/By A==; X-CSE-ConnectionGUID: MDSuwh6AQHmCUl56Xn+Nvw== X-CSE-MsgGUID: ysQnxE6kSUiiEXjJLx+Pjg== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="74636698" X-IronPort-AV: E=Sophos;i="6.21,262,1763452800"; d="scan'208";a="74636698" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 00:34:45 -0800 X-CSE-ConnectionGUID: NXLIdACVRh+NOjrpo883Sg== X-CSE-MsgGUID: lsWhnRsuSl+ZcVvqWu8o1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,262,1763452800"; d="scan'208";a="208910165" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 00:34:28 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, imre.deak@intel.com, Ankit Nautiyal Subject: [PATCH 14/17] drm/i915/dp: Account for DSC slice overhead Date: Fri, 30 Jan 2026 13:48:09 +0530 Message-ID: <20260130081812.32087-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260130081812.32087-1-ankit.k.nautiyal@intel.com> References: <20260130081812.32087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Account for DSC slice overhead bubbles and adjust the pixel rate while checking the pixel rate against the max dotclock limits. v2: Add missing assignment for dsc_slice_count in mst_connector_mode_valid_ctx(). (Imre) v3: Explicitly pass dsc_slice_count as 0 for Non-DSC case. (Imre) Signed-off-by: Ankit Nautiyal Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.c | 1 - drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ 5 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 61b86cdff3ef..3905723f5ab6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1414,6 +1414,8 @@ bool intel_dp_can_join(struct intel_display *display, bool intel_dp_dotclk_valid(struct intel_display *display, int target_clock, + int htotal, + int dsc_slice_count, int num_joined_pipes) { int max_dotclk = display->cdclk.max_dotclk_freq; @@ -1421,6 +1423,12 @@ bool intel_dp_dotclk_valid(struct intel_display *display, effective_dotclk_limit = max_dotclk * num_joined_pipes; + if (dsc_slice_count) + target_clock = intel_dsc_get_pixel_rate_with_dsc_bubbles(display, + target_clock, + htotal, + dsc_slice_count); + return target_clock <= effective_dotclk_limit; } @@ -1549,8 +1557,13 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (status != MODE_OK) continue; + if (!dsc) + dsc_slice_count = 0; + if (!intel_dp_dotclk_valid(display, target_clock, + mode->htotal, + dsc_slice_count, num_joined_pipes)) { status = MODE_CLOCK_HIGH; continue; @@ -2812,6 +2825,8 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder, if (ret || !intel_dp_dotclk_valid(display, adjusted_mode->crtc_clock, + adjusted_mode->crtc_htotal, + 0, num_joined_pipes)) dsc_needed = true; } @@ -2822,6 +2837,8 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder, } if (dsc_needed) { + int dsc_slice_count; + drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", str_yes_no(ret), str_yes_no(joiner_needs_dsc), @@ -2838,8 +2855,12 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder, if (ret < 0) return ret; + dsc_slice_count = intel_dsc_line_slice_count(&pipe_config->dsc.slice_config); + if (!intel_dp_dotclk_valid(display, adjusted_mode->crtc_clock, + adjusted_mode->crtc_htotal, + dsc_slice_count, num_joined_pipes)) return -EINVAL; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index edeb09372d1e..95a38763a367 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -226,6 +226,8 @@ bool intel_dp_can_join(struct intel_display *display, int num_joined_pipes); bool intel_dp_dotclk_valid(struct intel_display *display, int target_clock, + int htotal, + int dsc_slice_count, int num_joined_pipes); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0eab5ced27d3..ad66c483959b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -626,6 +626,8 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode if (ret || !intel_dp_dotclk_valid(display, adjusted_mode->clock, + adjusted_mode->htotal, + 0, num_joined_pipes)) dsc_needed = true; } @@ -637,6 +639,8 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode /* enable compression if the mode doesn't fit available BW */ if (dsc_needed) { + int dsc_slice_count; + drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); @@ -670,8 +674,12 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode if (ret) return ret; + dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, pipe_config); + if (!intel_dp_dotclk_valid(display, adjusted_mode->clock, + adjusted_mode->htotal, + dsc_slice_count, num_joined_pipes)) return -EINVAL; } @@ -1528,6 +1536,8 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, *status = MODE_CLOCK_HIGH; for (num_joined_pipes = 1; num_joined_pipes <= I915_MAX_PIPES; num_joined_pipes++) { + int dsc_slice_count = 0; + if (connector->force_joined_pipes && num_joined_pipes != connector->force_joined_pipes) continue; @@ -1546,6 +1556,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, */ int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); + dsc_slice_count = intel_dp_dsc_get_slice_count(connector, + mode->clock, + mode->hdisplay, + num_joined_pipes); + if (!drm_dp_is_uhbr_rate(max_link_clock)) bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC; @@ -1568,8 +1583,13 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, if (*status != MODE_OK) continue; + if (!dsc) + dsc_slice_count = 0; + if (!intel_dp_dotclk_valid(display, mode->clock, + mode->htotal, + dsc_slice_count, num_joined_pipes)) { *status = MODE_CLOCK_HIGH; continue; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 642a89270d8e..7e53201b3cb1 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1104,7 +1104,6 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } -static int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display, int pixel_rate, int htotal, int dsc_horizontal_slices) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index aeb17670307b..f4d5b37293cf 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -41,5 +41,8 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, const struct intel_crtc_state *crtc_state); int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state); unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state); +int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display, + int pixel_rate, int htotal, + int dsc_horizontal_slices); #endif /* __INTEL_VDSC_H__ */ -- 2.45.2