From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07C3AE87841 for ; Tue, 3 Feb 2026 15:48:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A3B7C10E1F9; Tue, 3 Feb 2026 15:48:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="n2alBxXu"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id D849310E1F9 for ; Tue, 3 Feb 2026 15:48:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770133736; x=1801669736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IaiX0ifzC5xUYLVr/0jsUFzc2mR2b0XB7zsgxGQ+baU=; b=n2alBxXuOm9zE9RdIt+HQHD4uJW2BlG6NBwk2mQvDtIIMvhJbg9KL1YT OQtSAVrlz8Bdu3N6CkgQ03hDiBMLQRbxPCI+L9R94Nj07xrfzM/N/bGan Bfp3Gq6LpMSI9hH+gOpAJJ0OTCR4VWtuKOSxntPQ6CzQu0A+upFRQad7L bE4tx/fB8Fryr6YG5fdPTxucUATLt30KOpLg9GYK1Wt1l4ZRvvpyzSauP /oGXiZYFXjv0UOKNd07waN8eAxtnotvT5dcQ4LBTnyVlTOzAYC1PQBVr8 YtQHl3UH2TrkUpAtyGGjK3BfW9r2qFUkk21fOrLlNxc2SuGkLHPE/7yOd Q==; X-CSE-ConnectionGUID: 4Mog4o+JRKKq2MmoKvTIJQ== X-CSE-MsgGUID: w7tvXYX+TrCOL0mTVPbxnA== X-IronPort-AV: E=McAfee;i="6800,10657,11690"; a="71207780" X-IronPort-AV: E=Sophos;i="6.21,270,1763452800"; d="scan'208";a="71207780" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2026 07:48:52 -0800 X-CSE-ConnectionGUID: 7XGHzM2PTUugolVMY+9fLw== X-CSE-MsgGUID: 12j5WRWIQ1mw+8h75HIezw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,270,1763452800"; d="scan'208";a="209918721" Received: from dut6094bmgfrd.fm.intel.com ([10.80.55.45]) by orviesa008.jf.intel.com with ESMTP; 03 Feb 2026 07:48:49 -0800 From: Jia Yao To: intel-xe@lists.freedesktop.org Cc: Jia Yao , stable@vger.kernel.org, Shuicheng Lin , Mathew Alwin , Michal Mrozek , Matthew Brost , Matthew Auld Subject: [PATCH v4] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Date: Tue, 3 Feb 2026 15:48:46 +0000 Message-ID: <20260203154846.1113521-1-jia.yao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129000147.339361-1-jia.yao@intel.com> References: <20260129000147.339361-1-jia.yao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add validation in xe_vm_madvise_ioctl() to reject PAT indices with XE_COH_NONE coherency mode when applied to CPU cached memory. Using coh_none with CPU cached buffers is a security issue. When the kernel clears pages before reallocation, the clear operation stays in CPU cache (dirty). GPU with coh_none can bypass CPU caches and read stale sensitive data directly from DRAM, potentially leaking data from previously freed pages of other processes. This aligns with the existing validation in vm_bind path (xe_vm_bind_ioctl_validate_bo). v2(Matthew brost) - Add fixes - Move one debug print to better place v3(Matthew Auld) - Should be drm/xe/uapi - More Cc v4(Shuicheng Lin) - Fix kmem leak issues by the way Fixes: ada7486c5668 ("drm/xe: Implement madvise ioctl for xe") Cc: stable@vger.kernel.org # v6.18 Cc: Shuicheng Lin Cc: Mathew Alwin Cc: Michal Mrozek Cc: Matthew Brost Cc: Matthew Auld Signed-off-by: Jia Yao --- drivers/gpu/drm/xe/xe_vm_madvise.c | 55 +++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c index add9a6ca2390..bf41fe75a336 100644 --- a/drivers/gpu/drm/xe/xe_vm_madvise.c +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c @@ -74,7 +74,7 @@ static int get_vmas(struct xe_vm *vm, struct xe_vmas_in_madvise_range *madvise_r } madvise_range->vmas[madvise_range->num_vmas] = vma; - (madvise_range->num_vmas)++; + madvise_range->num_vmas++; } if (!madvise_range->num_vmas) @@ -352,6 +352,43 @@ static void xe_madvise_details_fini(struct xe_madvise_details *details) drm_pagemap_put(details->dpagemap); } +static bool check_pat_args_are_sane(struct xe_device *xe, + struct xe_vmas_in_madvise_range *madvise_range, + u16 pat_index) +{ + u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); + int i; + + /* + * Using coh_none with CPU cached buffers is not allowed. + * Otherwise CPU page clearing can be bypassed, which is a + * security issue. GPU can directly access system memory and + * bypass CPU caches, potentially reading stale sensitive data + * from previously freed pages. + */ + if (coh_mode != XE_COH_NONE) + return true; + + for (i = 0; i < madvise_range->num_vmas; i++) { + struct xe_vma *vma = madvise_range->vmas[i]; + struct xe_bo *bo = xe_vma_bo(vma); + + if (bo) { + /* BO with WB caching + COH_NONE is not allowed */ + if (XE_IOCTL_DBG(xe, bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) + return false; + /* Imported dma-buf without caching info, assume cached */ + if (XE_IOCTL_DBG(xe, !bo->cpu_caching)) + return false; + } else if (XE_IOCTL_DBG(xe, xe_vma_is_cpu_addr_mirror(vma) || + xe_vma_is_userptr(vma))) + /* System memory (userptr/SVM) is always CPU cached */ + return false; + } + + return true; +} + static bool check_bo_args_are_sane(struct xe_vm *vm, struct xe_vma **vmas, int num_vmas, u32 atomic_val) { @@ -388,12 +425,12 @@ static bool check_bo_args_are_sane(struct xe_vm *vm, struct xe_vma **vmas, return true; } /** - * xe_vm_madvise_ioctl - Handle MADVise ioctl for a VM + * xe_vm_madvise_ioctl - Handle madvise ioctl for a VM * @dev: DRM device pointer * @data: Pointer to ioctl data (drm_xe_madvise*) * @file: DRM file pointer * - * Handles the MADVISE ioctl to provide memory advice for vma's within + * Handles the madvise ioctl to provide memory advice for vma's within * input range. * * Return: 0 on success or a negative error code on failure. @@ -442,13 +479,21 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil if (err || !madvise_range.num_vmas) goto madv_fini; + if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) { + if (!check_pat_args_are_sane(xe, &madvise_range, + args->pat_index.val)) { + err = -EINVAL; + goto free_vmas; + } + } + if (madvise_range.has_bo_vmas) { if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) { if (!check_bo_args_are_sane(vm, madvise_range.vmas, madvise_range.num_vmas, args->atomic.val)) { err = -EINVAL; - goto madv_fini; + goto free_vmas; } } @@ -485,8 +530,8 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil err_fini: if (madvise_range.has_bo_vmas) drm_exec_fini(&exec); +free_vmas: kfree(madvise_range.vmas); - madvise_range.vmas = NULL; madv_fini: xe_madvise_details_fini(&details); unlock_vm: -- 2.43.0