Re: [PATCH v2 3/4] drm/xe: Promote struct xe_tile definition to own file

[Matt Roper <matthew.d.roper@intel.com>]

On Tue, Feb 03, 2026 at 10:12:38PM +0100, Michal Wajdeczko wrote:
> We already have separate .c and .h files for xe_tile functions,
> time to introduce _types.h to follow what other components do.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
> v1: https://patchwork.freedesktop.org/patch/656886/?series=149807&rev=1
> v2: rebased, xe_vram_region already moved
> ---
>  drivers/gpu/drm/xe/xe_device_types.h | 129 +-----------------------
>  drivers/gpu/drm/xe/xe_tile_types.h   | 141 +++++++++++++++++++++++++++
>  2 files changed, 142 insertions(+), 128 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_tile_types.h
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 2ea931c1550a..14bf2c027f89 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,10 +15,6 @@
>  #include "xe_devcoredump_types.h"
>  #include "xe_heci_gsc.h"
>  #include "xe_late_bind_fw_types.h"
> -#include "xe_lmtt_types.h"
> -#include "xe_memirq_types.h"
> -#include "xe_mert.h"
> -#include "xe_mmio_types.h"
>  #include "xe_oa_types.h"
>  #include "xe_pagefault_types.h"
>  #include "xe_platform_types.h"
> @@ -30,7 +26,7 @@
>  #include "xe_sriov_vf_ccs_types.h"
>  #include "xe_step_types.h"
>  #include "xe_survivability_mode_types.h"
> -#include "xe_tile_sriov_vf_types.h"
> +#include "xe_tile_types.h"
>  #include "xe_validation.h"
>  
>  #if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
> @@ -96,129 +92,6 @@ enum xe_wedged_mode {
>  	 (_xe)->info.step.graphics >= (min_step) &&			\
>  	 (_xe)->info.step.graphics < (max_step))
>  
> -#define tile_to_xe(tile__)								\
> -	_Generic(tile__,								\
> -		 const struct xe_tile * : (const struct xe_device *)((tile__)->xe),	\
> -		 struct xe_tile * : (tile__)->xe)
> -
> -/**
> - * struct xe_tile - hardware tile structure
> - *
> - * From a driver perspective, a "tile" is effectively a complete GPU, containing
> - * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
> - *
> - * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
> - * device and designate one "root" tile as being responsible for external PCI
> - * communication.  PCI BAR0 exposes the GGTT and MMIO register space for each
> - * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
> - * with each tile similarly.  Device-wide interrupts can be enabled/disabled
> - * at the root tile, and the MSTR_TILE_INTR register will report which tiles
> - * have interrupts that need servicing.
> - */
> -struct xe_tile {
> -	/** @xe: Backpointer to tile's PCI device */
> -	struct xe_device *xe;
> -
> -	/** @id: ID of the tile */
> -	u8 id;
> -
> -	/**
> -	 * @primary_gt: Primary GT
> -	 */
> -	struct xe_gt *primary_gt;
> -
> -	/**
> -	 * @media_gt: Media GT
> -	 *
> -	 * Only present on devices with media version >= 13.
> -	 */
> -	struct xe_gt *media_gt;
> -
> -	/**
> -	 * @mmio: MMIO info for a tile.
> -	 *
> -	 * Each tile has its own 16MB space in BAR0, laid out as:
> -	 * * 0-4MB: registers
> -	 * * 4MB-8MB: reserved
> -	 * * 8MB-16MB: global GTT
> -	 */
> -	struct xe_mmio mmio;
> -
> -	/** @mem: memory management info for tile */
> -	struct {
> -		/**
> -		 * @mem.kernel_vram: kernel-dedicated VRAM info for tile.
> -		 *
> -		 * Although VRAM is associated with a specific tile, it can
> -		 * still be accessed by all tiles' GTs.
> -		 */
> -		struct xe_vram_region *kernel_vram;
> -
> -		/**
> -		 * @mem.vram: general purpose VRAM info for tile.
> -		 *
> -		 * Although VRAM is associated with a specific tile, it can
> -		 * still be accessed by all tiles' GTs.
> -		 */
> -		struct xe_vram_region *vram;
> -
> -		/** @mem.ggtt: Global graphics translation table */
> -		struct xe_ggtt *ggtt;
> -
> -		/**
> -		 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
> -		 *
> -		 * Media GT shares a pool with its primary GT.
> -		 */
> -		struct xe_sa_manager *kernel_bb_pool;
> -
> -		/**
> -		 * @mem.reclaim_pool: Pool for PRLs allocated.
> -		 *
> -		 * Only main GT has page reclaim list allocations.
> -		 */
> -		struct xe_sa_manager *reclaim_pool;
> -	} mem;
> -
> -	/** @sriov: tile level virtualization data */
> -	union {
> -		struct {
> -			/** @sriov.pf.lmtt: Local Memory Translation Table. */
> -			struct xe_lmtt lmtt;
> -		} pf;
> -		struct {
> -			/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
> -			struct xe_ggtt_node *ggtt_balloon[2];
> -			/** @sriov.vf.self_config: VF configuration data */
> -			struct xe_tile_sriov_vf_selfconfig self_config;
> -		} vf;
> -	} sriov;
> -
> -	/** @memirq: Memory Based Interrupts. */
> -	struct xe_memirq memirq;
> -
> -	/** @csc_hw_error_work: worker to report CSC HW errors */
> -	struct work_struct csc_hw_error_work;
> -
> -	/** @pcode: tile's PCODE */
> -	struct {
> -		/** @pcode.lock: protecting tile's PCODE mailbox data */
> -		struct mutex lock;
> -	} pcode;
> -
> -	/** @migrate: Migration helper for vram blits and clearing */
> -	struct xe_migrate *migrate;
> -
> -	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
> -	struct kobject *sysfs;
> -
> -	/** @debugfs: debugfs directory associated with this tile */
> -	struct dentry *debugfs;
> -
> -	/** @mert: MERT-related data */
> -	struct xe_mert mert;
> -};
> -
>  /**
>   * struct xe_device - Top level struct of Xe device
>   */
> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
> new file mode 100644
> index 000000000000..33932fd547d7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022-2026 Intel Corporation
> + */
> +
> +#ifndef _XE_TILE_TYPES_H_
> +#define _XE_TILE_TYPES_H_
> +
> +#include <linux/mutex_types.h>
> +#include <linux/workqueue_types.h>
> +
> +#include "xe_lmtt_types.h"
> +#include "xe_memirq_types.h"
> +#include "xe_mert.h"
> +#include "xe_mmio_types.h"
> +#include "xe_tile_sriov_vf_types.h"
> +
> +#define tile_to_xe(tile__)								\
> +	_Generic(tile__,								\
> +		 const struct xe_tile * : (const struct xe_device *)((tile__)->xe),	\
> +		 struct xe_tile * : (tile__)->xe)
> +
> +/**
> + * struct xe_tile - hardware tile structure
> + *
> + * From a driver perspective, a "tile" is effectively a complete GPU, containing
> + * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
> + *
> + * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
> + * device and designate one "root" tile as being responsible for external PCI
> + * communication.  PCI BAR0 exposes the GGTT and MMIO register space for each
> + * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
> + * with each tile similarly.  Device-wide interrupts can be enabled/disabled
> + * at the root tile, and the MSTR_TILE_INTR register will report which tiles
> + * have interrupts that need servicing.
> + */
> +struct xe_tile {
> +	/** @xe: Backpointer to tile's PCI device */
> +	struct xe_device *xe;
> +
> +	/** @id: ID of the tile */
> +	u8 id;
> +
> +	/**
> +	 * @primary_gt: Primary GT
> +	 */
> +	struct xe_gt *primary_gt;
> +
> +	/**
> +	 * @media_gt: Media GT
> +	 *
> +	 * Only present on devices with media version >= 13.
> +	 */
> +	struct xe_gt *media_gt;
> +
> +	/**
> +	 * @mmio: MMIO info for a tile.
> +	 *
> +	 * Each tile has its own 16MB space in BAR0, laid out as:
> +	 * * 0-4MB: registers
> +	 * * 4MB-8MB: reserved
> +	 * * 8MB-16MB: global GTT
> +	 */
> +	struct xe_mmio mmio;
> +
> +	/** @mem: memory management info for tile */
> +	struct {
> +		/**
> +		 * @mem.kernel_vram: kernel-dedicated VRAM info for tile.
> +		 *
> +		 * Although VRAM is associated with a specific tile, it can
> +		 * still be accessed by all tiles' GTs.
> +		 */
> +		struct xe_vram_region *kernel_vram;
> +
> +		/**
> +		 * @mem.vram: general purpose VRAM info for tile.
> +		 *
> +		 * Although VRAM is associated with a specific tile, it can
> +		 * still be accessed by all tiles' GTs.
> +		 */
> +		struct xe_vram_region *vram;
> +
> +		/** @mem.ggtt: Global graphics translation table */
> +		struct xe_ggtt *ggtt;
> +
> +		/**
> +		 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
> +		 *
> +		 * Media GT shares a pool with its primary GT.
> +		 */
> +		struct xe_sa_manager *kernel_bb_pool;
> +
> +		/**
> +		 * @mem.reclaim_pool: Pool for PRLs allocated.
> +		 *
> +		 * Only main GT has page reclaim list allocations.
> +		 */
> +		struct xe_sa_manager *reclaim_pool;
> +	} mem;
> +
> +	/** @sriov: tile level virtualization data */
> +	union {
> +		struct {
> +			/** @sriov.pf.lmtt: Local Memory Translation Table. */
> +			struct xe_lmtt lmtt;
> +		} pf;
> +		struct {
> +			/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
> +			struct xe_ggtt_node *ggtt_balloon[2];
> +			/** @sriov.vf.self_config: VF configuration data */
> +			struct xe_tile_sriov_vf_selfconfig self_config;
> +		} vf;
> +	} sriov;
> +
> +	/** @memirq: Memory Based Interrupts. */
> +	struct xe_memirq memirq;
> +
> +	/** @csc_hw_error_work: worker to report CSC HW errors */
> +	struct work_struct csc_hw_error_work;
> +
> +	/** @pcode: tile's PCODE */
> +	struct {
> +		/** @pcode.lock: protecting tile's PCODE mailbox data */
> +		struct mutex lock;
> +	} pcode;
> +
> +	/** @migrate: Migration helper for vram blits and clearing */
> +	struct xe_migrate *migrate;
> +
> +	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
> +	struct kobject *sysfs;
> +
> +	/** @debugfs: debugfs directory associated with this tile */
> +	struct dentry *debugfs;
> +
> +	/** @mert: MERT-related data */
> +	struct xe_mert mert;
> +};
> +
> +#endif
> -- 
> 2.47.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation