From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E5AFEF99E0 for ; Fri, 13 Feb 2026 22:34:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CDDE910E862; Fri, 13 Feb 2026 22:34:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NTNJhhcK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id D6FA310E858; Fri, 13 Feb 2026 22:34:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771022054; x=1802558054; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m3n/PxRy4zheNZQJS7oIbI7QwHbljPYk56Zz1da4Ipg=; b=NTNJhhcKRRvmZih+NJV8Nd7EkgGcmXSDQzSoUPqWu7vIzhLrMgkXbJLO 9EP8RxJzF1WlwuL+E7dI45+sKRyhxGJnN5LQkXho+GYusGNFixNRsZGm5 sgyLwiN2PHF8BTIyBShgxYx0P8yE+zOjboD8BK5OPEbYKsEXM2T2VCqcR VywzFqXe5lQ6FDm/x6aYjC9pCthIjsJm+UFLBwPLq2If4QRd7Nywsaj+Z RsbJwF+8I8z+ACl8617WmIZ2hVontHCOeaqckn1ruKfAqQ2mROthNK88j pys/49GVaJua5aEh8HJCcoVh290Ri/sJ5zUlISfc1bstTLw6uR/gJF2c8 g==; X-CSE-ConnectionGUID: IxFwQtC9RZuBMua77UUcxg== X-CSE-MsgGUID: OTdiY8AtRTaC8L+1FAHbpA== X-IronPort-AV: E=McAfee;i="6800,10657,11700"; a="94844920" X-IronPort-AV: E=Sophos;i="6.21,289,1763452800"; d="scan'208";a="94844920" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2026 14:34:14 -0800 X-CSE-ConnectionGUID: 6cw1mYwnQFCqQhHICle7jw== X-CSE-MsgGUID: bYxQGCsAQ8CUCmzwshYbJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,289,1763452800"; d="scan'208";a="250698299" Received: from dut4086lnl.fm.intel.com ([10.105.11.7]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2026 14:34:14 -0800 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, ivan.briano@intel.com, matthew.auld@intel.com, dafna.hirschfeld@intel.com Subject: [PATCH v34 2/6] drm/xe/xe_pagefault: Pack engine class instance into u8 Date: Fri, 13 Feb 2026 22:34:13 +0000 Message-ID: <20260213223410.99613-10-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260213223410.99613-8-jonathan.cavitt@intel.com> References: <20260213223410.99613-8-jonathan.cavitt@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Pack the engine class and instance fields into a single u8 to save space in struct xe_pagefault. The saved space will be used later to store something else. Suggested-by: Matthew Brost Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/xe/xe_guc_pagefault.c | 7 +++++-- drivers/gpu/drm/xe/xe_pagefault.c | 11 +++++++---- drivers/gpu/drm/xe/xe_pagefault_types.h | 16 ++++++++++++---- 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc_pagefault.c b/drivers/gpu/drm/xe/xe_guc_pagefault.c index d48f6ed103bb..8eaa1dfc1e66 100644 --- a/drivers/gpu/drm/xe/xe_guc_pagefault.c +++ b/drivers/gpu/drm/xe/xe_guc_pagefault.c @@ -85,8 +85,11 @@ int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len) FIELD_GET(PFD_FAULT_LEVEL, msg[0])) | FIELD_PREP(XE_PAGEFAULT_TYPE_MASK, FIELD_GET(PFD_FAULT_TYPE, msg[2])); - pf.consumer.engine_class = FIELD_GET(PFD_ENG_CLASS, msg[0]); - pf.consumer.engine_instance = FIELD_GET(PFD_ENG_INSTANCE, msg[0]); + pf.consumer.engine_class_instance = + FIELD_PREP(XE_PAGEFAULT_ENGINE_CLASS_MASK, + FIELD_GET(PFD_ENG_CLASS, msg[0])) | + FIELD_PREP(XE_PAGEFAULT_ENGINE_INSTANCE_MASK, + FIELD_GET(PFD_ENG_INSTANCE, msg[0])); pf.producer.private = guc; pf.producer.ops = &guc_pagefault_ops; diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c index 0281b5b6d4ab..47b6a7628dc1 100644 --- a/drivers/gpu/drm/xe/xe_pagefault.c +++ b/drivers/gpu/drm/xe/xe_pagefault.c @@ -229,13 +229,15 @@ static bool xe_pagefault_queue_pop(struct xe_pagefault_queue *pf_queue, static void xe_pagefault_print(struct xe_pagefault *pf) { + enum xe_engine_class class = FIELD_GET(XE_PAGEFAULT_ENGINE_CLASS_MASK, + pf->consumer.engine_class_instance); xe_gt_info(pf->gt, "\n\tASID: %d\n" "\tFaulted Address: 0x%08x%08x\n" "\tFaultType: %lu\n" "\tAccessType: %d\n" "\tFaultLevel: %lu\n" "\tEngineClass: %d %s\n" - "\tEngineInstance: %d\n", + "\tEngineInstance: %lu\n", pf->consumer.asid, upper_32_bits(pf->consumer.page_addr), lower_32_bits(pf->consumer.page_addr), @@ -244,9 +246,10 @@ static void xe_pagefault_print(struct xe_pagefault *pf) pf->consumer.access_type, FIELD_GET(XE_PAGEFAULT_LEVEL_MASK, pf->consumer.fault_type_level), - pf->consumer.engine_class, - xe_hw_engine_class_to_str(pf->consumer.engine_class), - pf->consumer.engine_instance); + class, + xe_hw_engine_class_to_str(class), + FIELD_GET(XE_PAGEFAULT_ENGINE_INSTANCE_MASK, + pf->consumer.engine_class_instance)); } static void xe_pagefault_queue_work(struct work_struct *w) diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h index 0e378f41ede6..a14725a02f39 100644 --- a/drivers/gpu/drm/xe/xe_pagefault_types.h +++ b/drivers/gpu/drm/xe/xe_pagefault_types.h @@ -80,10 +80,18 @@ struct xe_pagefault { #define XE_PAGEFAULT_TYPE_LEVEL_NACK 0xff /* Producer indicates nack fault */ #define XE_PAGEFAULT_LEVEL_MASK GENMASK(3, 0) #define XE_PAGEFAULT_TYPE_MASK GENMASK(7, 4) - /** @consumer.engine_class: engine class */ - u8 engine_class; - /** @consumer.engine_instance: engine instance */ - u8 engine_instance; + /** + * @consumer.engine_class_instance: engine class and instance, packed + * into a single u8 to keep compact + */ + u8 engine_class_instance; +#define XE_PAGEFAULT_ENGINE_CLASS_MASK GENMASK(3, 0) +#define XE_PAGEFAULT_ENGINE_INSTANCE_MASK GENMASK(7, 4) + /** + * consumer.align: buffer u8 to keep struct aligned to u64. + * Will be used later to store data. + */ + u8 align; /** consumer.reserved: reserved bits for future expansion */ u64 reserved; } consumer; -- 2.43.0