* [PATCH v3 0/2] Update the PHY timeouts
@ 2026-02-16 4:59 Arun R Murthy
2026-02-16 4:59 ` [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time Arun R Murthy
2026-02-16 4:59 ` [PATCH v3 2/2] drm/i915/lt_phy_regs: Add SoC/OS " Arun R Murthy
0 siblings, 2 replies; 6+ messages in thread
From: Arun R Murthy @ 2026-02-16 4:59 UTC (permalink / raw)
To: Jani Nikula, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy, Cole Leavitt
The timeouts mentioned in the spec is the recommendation from the PHY
and doesnt include the turnaround time of SoC and the OS. So ensure that
sufficient overhead is added for SoC and OS along with the PHY
recommended timeouts.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Changes in v3:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v2: https://lore.kernel.org/r/20260212-timeout-v2-0-74bccad5018d@intel.com
Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20260212-timeout-v1-0-591fa766e8a1@intel.com
---
Arun R Murthy (2):
drm/i915/cx0_phy_regs: Include SoC and OS turnaround time
drm/i915/lt_phy_regs: Add SoC/OS turnaround time
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: b4bfe7d753afaf6ea4950111a309a4e2ef5aef68
change-id: 20260212-timeout-06cb232f71af
Best regards,
--
Arun R Murthy <arun.r.murthy@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time
2026-02-16 4:59 [PATCH v3 0/2] Update the PHY timeouts Arun R Murthy
@ 2026-02-16 4:59 ` Arun R Murthy
2026-02-23 10:37 ` Jani Nikula
2026-02-16 4:59 ` [PATCH v3 2/2] drm/i915/lt_phy_regs: Add SoC/OS " Arun R Murthy
1 sibling, 1 reply; 6+ messages in thread
From: Arun R Murthy @ 2026-02-16 4:59 UTC (permalink / raw)
To: Jani Nikula, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy, Cole Leavitt
The port refclk enable timeout and the soc ready timeout value mentioned
in the spec is the PHY timings and doesn't include the turnaround time
from the SoC or OS. So add an overhead timeout value on top of the
recommended timeouts from the PHY spec.
The overhead value is based on the stress test results with multiple
available panels.
Reported-by: Cole Leavitt <cole@unwrap.rs>
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14713
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714a2bd2d6612cbbd4698 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -78,10 +78,10 @@
#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
-#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
+#define XELPDP_PORT_RESET_START_TIMEOUT_US 10
#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS 2
#define XELPDP_PORT_RESET_END_TIMEOUT_MS 15
-#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
+#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10
#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] drm/i915/lt_phy_regs: Add SoC/OS turnaround time
2026-02-16 4:59 [PATCH v3 0/2] Update the PHY timeouts Arun R Murthy
2026-02-16 4:59 ` [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time Arun R Murthy
@ 2026-02-16 4:59 ` Arun R Murthy
2026-02-23 10:38 ` Jani Nikula
1 sibling, 1 reply; 6+ messages in thread
From: Arun R Murthy @ 2026-02-16 4:59 UTC (permalink / raw)
To: Jani Nikula, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy
On top the timeouts mentioned in the spec which includes only the PHY
timeouts include the SoC and the OS turnaround time.
The overhead value is based on the stress test results with multiple
available panels.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 37e46fb9abde4156ebd7ad1eb6cbbc12e7026b23..ff6d7829dbb9c50b2001d079b435b894faf9659e 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -6,12 +6,12 @@
#ifndef __INTEL_LT_PHY_REGS_H__
#define __INTEL_LT_PHY_REGS_H__
-#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
+#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
#define XE3PLPD_MACCLK_TURNON_LATENCY_MS 2
-#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1
+#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 10
#define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS 1
-#define XE3PLPD_RESET_START_LATENCY_US 10
-#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 4
+#define XE3PLPD_RESET_START_LATENCY_US 10
+#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 10
#define XE3PLPD_RESET_END_LATENCY_MS 2
/* LT Phy MAC Register */
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time
2026-02-16 4:59 ` [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time Arun R Murthy
@ 2026-02-23 10:37 ` Jani Nikula
2026-02-24 2:41 ` Kandpal, Suraj
0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2026-02-23 10:37 UTC (permalink / raw)
To: Arun R Murthy, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy, Cole Leavitt
On Mon, 16 Feb 2026, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> The port refclk enable timeout and the soc ready timeout value mentioned
> in the spec is the PHY timings and doesn't include the turnaround time
> from the SoC or OS. So add an overhead timeout value on top of the
> recommended timeouts from the PHY spec.
> The overhead value is based on the stress test results with multiple
> available panels.
>
> Reported-by: Cole Leavitt <cole@unwrap.rs>
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14713
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714a2bd2d6612cbbd4698 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -78,10 +78,10 @@
> #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
> #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
> #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
> -#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
> +#define XELPDP_PORT_RESET_START_TIMEOUT_US 10
> #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS 2
> #define XELPDP_PORT_RESET_END_TIMEOUT_MS 15
> -#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
> +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10
Side note, *none* of these belong in intel_cx0_phy_regs.h. They should
be moved to intel_cx0_phy.c instead.
The timeouts do not describe the register contents.
BR,
Jani.
>
> #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
> #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/lt_phy_regs: Add SoC/OS turnaround time
2026-02-16 4:59 ` [PATCH v3 2/2] drm/i915/lt_phy_regs: Add SoC/OS " Arun R Murthy
@ 2026-02-23 10:38 ` Jani Nikula
0 siblings, 0 replies; 6+ messages in thread
From: Jani Nikula @ 2026-02-23 10:38 UTC (permalink / raw)
To: Arun R Murthy, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy
On Mon, 16 Feb 2026, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> On top the timeouts mentioned in the spec which includes only the PHY
> timeouts include the SoC and the OS turnaround time.
> The overhead value is based on the stress test results with multiple
> available panels.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 37e46fb9abde4156ebd7ad1eb6cbbc12e7026b23..ff6d7829dbb9c50b2001d079b435b894faf9659e 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -6,12 +6,12 @@
> #ifndef __INTEL_LT_PHY_REGS_H__
> #define __INTEL_LT_PHY_REGS_H__
>
> -#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
> +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
> #define XE3PLPD_MACCLK_TURNON_LATENCY_MS 2
> -#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1
> +#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 10
> #define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS 1
> -#define XE3PLPD_RESET_START_LATENCY_US 10
> -#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 4
> +#define XE3PLPD_RESET_START_LATENCY_US 10
> +#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 10
> #define XE3PLPD_RESET_END_LATENCY_MS 2
Side note, *none* of these belong in intel_lt_phy_regs.h. They should be
moved to intel_lt_phy.c instead.
The timeouts do not describe the register contents.
BR,
Jani.
>
> /* LT Phy MAC Register */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time
2026-02-23 10:37 ` Jani Nikula
@ 2026-02-24 2:41 ` Kandpal, Suraj
0 siblings, 0 replies; 6+ messages in thread
From: Kandpal, Suraj @ 2026-02-24 2:41 UTC (permalink / raw)
To: Jani Nikula, Murthy, Arun R, Shankar, Uma, Nautiyal, Ankit K
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Murthy, Arun R, Cole Leavitt
> Subject: Re: [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS
> turnaround time
>
> On Mon, 16 Feb 2026, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > The port refclk enable timeout and the soc ready timeout value
> > mentioned in the spec is the PHY timings and doesn't include the
> > turnaround time from the SoC or OS. So add an overhead timeout value
> > on top of the recommended timeouts from the PHY spec.
> > The overhead value is based on the stress test results with multiple
> > available panels.
> >
> > Reported-by: Cole Leavitt <cole@unwrap.rs>
> > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14713
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > index
> >
> 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714
> a2bd2d
> > 6612cbbd4698 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > @@ -78,10 +78,10 @@
> > #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
> > #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
> > #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
> > -#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
> > +#define XELPDP_PORT_RESET_START_TIMEOUT_US 10
> > #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS
> 2
> > #define XELPDP_PORT_RESET_END_TIMEOUT_MS 15
> > -#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
> > +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10
>
> Side note, *none* of these belong in intel_cx0_phy_regs.h. They should be
> moved to intel_cx0_phy.c instead.
>
> The timeouts do not describe the register contents.
Hi ,
Jani you are right these need to be moved into intel_cx0_phy.c and the same for the next patch thanks for pointing that out.
Ill work on a new series and send that out along with some other things that may need to be moved.
Currently merging this to close the gitlab issue and have this fix land in din
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
> >
> > #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
> > #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-02-16 4:59 [PATCH v3 0/2] Update the PHY timeouts Arun R Murthy
2026-02-16 4:59 ` [PATCH v3 1/2] drm/i915/cx0_phy_regs: Include SoC and OS turnaround time Arun R Murthy
2026-02-23 10:37 ` Jani Nikula
2026-02-24 2:41 ` Kandpal, Suraj
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