From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C15CCEEF309 for ; Thu, 5 Mar 2026 06:36:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E36210E20E; Thu, 5 Mar 2026 06:36:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B0G+6tOm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE1E510E20E for ; Thu, 5 Mar 2026 06:36:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772692565; x=1804228565; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=O1p1p/b1MbCd/Ytc/9oqOfWX98iG5JkvGhu3TaPmPxI=; b=B0G+6tOm1iRUygZRmpTFpPdZzHJ9a1aqKsd7o6BwQx5zl2SOL1/5Boil QpVmUlszhV05GsCQvXA6FqmNrA8d9eueOCPA8/EKnuM1wOhZVKNrYi2KO TdsHhAYjxbZDU1DyEn8Vh0NXGxH6Gc8doR8xmXuyDrnlJXpoZ6sK7AYKf uxmEHc3m+dXuQV1BvNn3MI4yP96V2Z47sP19ARdZcbGoxAOEM4Lr1b3iG VfgBljbf95FWnQf2jsBbc/RQgNCGCNfJDTzyexDhobgsP0JHYeO4ukuYv 4djWSRkb8cze+/iIEVNpJhov3j0QFQv6M75qjaHWiJEa4b0mWjxd6DjWu g==; X-CSE-ConnectionGUID: CQVikqTISfyYZkQyni/MJg== X-CSE-MsgGUID: FitBLnftToKFnzfWcF+cJQ== X-IronPort-AV: E=McAfee;i="6800,10657,11719"; a="73469872" X-IronPort-AV: E=Sophos;i="6.21,325,1763452800"; d="scan'208";a="73469872" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2026 22:36:05 -0800 X-CSE-ConnectionGUID: pUdaIeqHQheomwt4tk90ow== X-CSE-MsgGUID: 5b7rrV4oSE+NIovmS69ngg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,325,1763452800"; d="scan'208";a="249050596" Received: from varungup-desk.iind.intel.com ([10.190.238.71]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2026 22:36:02 -0800 From: Varun Gupta To: intel-xe@lists.freedesktop.org Cc: matthew.d.roper@intel.com, tejas.upadhyay@intel.com Subject: [PATCH v3] drm/xe: Add Wa_14026578760 Date: Thu, 5 Mar 2026 12:05:53 +0530 Message-ID: <20260305063553.3665044-1-varun.gupta@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add GT workaround Wa_14026578760 for graphics versions 35.10, 35.11 and media version 35.03. Signed-off-by: Varun Gupta --- v3: - Use separate register defines for graphics and media (Tejas) v2: - Fix register define ordering (Matt Roper) - Broaden workaround scope to cover graphics 35.10, 35.11 and media 35.03 per workaround database (Matt Roper) --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++ drivers/gpu/drm/xe/xe_wa.c | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 90b9017770ea..c4da4a5c02a5 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -100,6 +100,11 @@ #define VE1_AUX_INV XE_REG(0x42b8) #define AUX_INV REG_BIT(0) +#define GAMSTLB_CTRL 0x477c +#define GAMSTLB_CTRL_MEDIA XE_REG(GAMSTLB_CTRL + MEDIA_GT_GSI_OFFSET) +#define GAMSTLB_CTRL_3D XE_REG_MCR(GAMSTLB_CTRL) +#define DIS_PEND_GPA_LINK REG_BIT(13) + #define GAMSTLB_CTRL2 XE_REG_MCR(0x4788) #define STLB_SINGLE_BANK_MODE REG_BIT(11) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 26950b8a7543..fe6e42517799 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -164,6 +164,10 @@ static const struct xe_rtp_entry_sr gt_was[] = { MEDIA_VERSION_RANGE(1301, 3500)), XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) }, + { XE_RTP_NAME("14026578760"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, 3511)), + XE_RTP_ACTIONS(SET(GAMSTLB_CTRL_3D, DIS_PEND_GPA_LINK)) + }, /* DG1 */ @@ -303,6 +307,13 @@ static const struct xe_rtp_entry_sr gt_was[] = { XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)), XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES)) }, + + /* Xe3P_HPM */ + + { XE_RTP_NAME("14026578760"), + XE_RTP_RULES(MEDIA_VERSION(3503)), + XE_RTP_ACTIONS(SET(GAMSTLB_CTRL_MEDIA, DIS_PEND_GPA_LINK)) + }, }; static const struct xe_rtp_entry_sr engine_was[] = { -- 2.43.0