[PATCH v4 0/2] Enable seamless boot (fastboot) for PTL

[Juasheem Sultan <jdsultan@google.com>]

This is the fourth version of a series of patches meant to add
support for seamless framebuffer handoff within the Xe driver. 
It was tested on Panther Lake platforms.

The goal of this series is to achieve a flicker-free transition from
the bootloader (BIOS/UEFI) to the kernel driver by strictly adhering
to the hardware state established by the firmware.

With this version, I've taken the feedback that the last version was
doing too broad of a copy of the hardware crtc state into the new 
atomic state. Rather than that, we are now instead sanitizing the 
clock values and pll state. 

The BIOS appears to set a slightly different clock than the ideal value
calculated by the driver. If these are within a small tolerance of each
other then we adopt the BIOS clock values. 

The pll state that the driver reads has bytes 4 to 8 programmed to 0
in non-ssc registers. The state read from the hardware doesn't have 
this, so we adopt the hardware state if they match without those bytes.

---
Changes since v1
- v2 Complete rewrite of the code
- v3 Resending due to failure of patches to send
- v4 Switched from complete state copy to clock sanitization

Juasheem Sultan (2):
  drm/xe/display: Fix reading the framebuffer from stolen memory
  drm/i915/display: Sync state to BIOS for seamless handoff

 drivers/gpu/drm/i915/display/intel_display.c  | 67 +++++++++++++++++++
 drivers/gpu/drm/xe/display/xe_initial_plane.c | 22 +++++-
 2 files changed, 88 insertions(+), 1 deletion(-)

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2.53.0.851.ga537e3e6e9-goog