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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 7/9] drm/i915/wm: Verify 'ddb_y' as well as 'ddb'
Date: Tue, 24 Mar 2026 15:48:41 +0200	[thread overview]
Message-ID: <20260324134843.2364-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20260324134843.2364-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Verify the pre-icl NV12 Y color plane DDB entry. Thus far
we've only verified the RGB/UV DDB entry.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 17faf090a154..1d932c37d768 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -4022,6 +4022,10 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
 		skl_ddb_entry_verify(plane, "DDB",
 				     &hw->ddb[plane->id],
 				     &new_crtc_state->wm.skl.plane_ddb[plane->id]);
+
+		skl_ddb_entry_verify(plane, "DDB Y",
+				     &hw->ddb_y[plane->id],
+				     &new_crtc_state->wm.skl.plane_ddb_y[plane->id]);
 	}
 
 	kfree(hw);
-- 
2.52.0


  parent reply	other threads:[~2026-03-24 13:49 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-24 13:48 [PATCH 0/9] drm/i915/wm: Watermark/SAGV fixes/cleanups/etc Ville Syrjala
2026-03-24 13:48 ` [PATCH 1/9] drm/i915/wm: Reject SAGV consistently when block_time_us==0 Ville Syrjala
2026-04-08  9:56   ` Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 2/9] drm/i915/wm: Don't compute separate SAGV watermarks for RKL Ville Syrjala
2026-04-08 11:48   ` Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 3/9] drm/i915/wm: Consolidate SAGV pipe active/interlace checks to common code Ville Syrjala
2026-04-08 11:49   ` Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 4/9] drm/i915/wm: Verify the correct plane DDB entry Ville Syrjala
2026-04-08 11:53   ` Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 5/9] drm/i915/wm: Extract skl_wm_level_verify() Ville Syrjala
2026-04-08 11:55   ` Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 6/9] drm/i915/wm: Extract skl_ddb_entry_verify() Ville Syrjala
2026-04-08 11:57   ` Govindapillai, Vinod
2026-03-24 13:48 ` Ville Syrjala [this message]
2026-04-08 11:59   ` [PATCH 7/9] drm/i915/wm: Verify 'ddb_y' as well as 'ddb' Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 8/9] drm/i915/wm: Reduce copy-pasta in skl_print_plane_wm_changes() Ville Syrjala
2026-04-08 12:04   ` Govindapillai, Vinod
2026-03-24 13:48 ` [PATCH 9/9] drm/i915/wm: Allow SAGV with multiple pipes on pre-icl Ville Syrjala
2026-04-08 12:10   ` Govindapillai, Vinod
2026-03-24 13:58 ` ✗ CI.checkpatch: warning for drm/i915/wm: Watermark/SAGV fixes/cleanups/etc Patchwork
2026-03-24 14:00 ` ✓ CI.KUnit: success " Patchwork
2026-03-24 14:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-25  2:08 ` ✓ Xe.CI.FULL: " Patchwork

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